PLECS 3.2 Online Help

D Flip-flop

Purpose

Implement edge-triggered flip-flop

Library

Control / Logical

Description

pict

The D flip-flop sets its output Q to the value of its input D when an edge on the clock input is detected. The behavior is shown in the following truth table:

DClkQ/Q
00No changeNo change
01No changeNo change
10No changeNo change
11No changeNo change
0Triggering edge01
1Triggering edge10

The input D is latched, i.e. when a triggering edge in the clock signal is detected the value of D from the previous simulation step is used to set the output. In other words, D must be stable for at least one simulation step before the flip-flop is triggered by the clock signal.

Parameter

Trigger edge
The direction of the edge on which the D input is read.

Probe Signals

D
The input signal D.
Clk
The clock input signal.
Q
The output signals Q.
/Q
The output signals /Q.