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Implement set-reset flip-flop
Control / Logical
The SR Flip-flop behaves like a pair of cross-coupled NOR logic gates. The output values correspond to the following truth table:
S | R | Q | /Q |
0 | 0 | No change | No change |
0 | 1 | 0 | 1 |
1 | 0 | 1 | 0 |
1 | 1 | Restricted (0) | Restricted (0) |
The combination S = R = 1 is restricted because both outputs will be set to 0, violating the condition Q = not(/Q). If both inputs change from 1 to 0 in the same simulation step, Q will be set to 0 and /Q to 1.