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TI C2000 Peripheral Models

Introduction

Microcontrollers (MCUs) for control applications typically contain peripheral modules such as Analog-to-Digital Converters (ADCs) and pulse width modulators (PWMs). These peripherals play an important role, since they act as the interface between the digital/analog signals of the control hardware and the control algorithms running on the processor. State-of-the-art MCUs often include peripherals with a multitude of advanced features and configurations to help implement complex sampling and modulation techniques.

When modeling power converters in a circuit simulator such as PLECS, it is desirable to represent the behavior of the MCU peripherals as accurately as possible. Basic Sample&Hold blocks and PWM modulators are useful for higher-level modeling. However, important details with regards to timing and quantization are lost when attempting to model an ADC with a basic zero-order hold (ZOH) block. For example, employing an idealized modulator to generate PWM signals can result in simulation results substantially different from the real hardware behavior.

Accurate peripheral models are even more important in the context of Processor-In-the-Loop (PIL) simulations. In this case, it is imperative to utilize peripheral models which are configurable exactly as the real implementations, i.e. by setting values in peripheral registers. By the same token, the inputs and outputs of the peripheral models must correspond precisely to the numerical representation in the embedded code.

The PLECS PIL library includes high-fidelity MCU peripheral models which work at the register level, and are therefore well-suited for PIL simulations. Furthermore, certain blocks have a second implementation with a graphical user interface (GUI) that automatically determines the register configurations based on text-based parameter selections.

Subsequent sections describe the PLECS peripheral components in detail and highlight modeling assumptions and limitations. When documenting peripheral register settings, the following color coding is used:

  1. Grey (dark shading): No effect on the model behavior
  2. Green (light shading): Register cell affects the behavior of the model

Enhanced Pulse Width Modulator (ePWM) Type 1

The PLECS peripheral library provides two blocks for the TI ePWM type 0/1 module. One block has a register-based configuration mask and a second block features a graphical user interface. In both cases, you should distinguish between registers configured in the parameter mask and inputs to the block. Mask parameters are fixed (static) during simulation and correspond to the configurations which the embedded software makes during the initialization phase. Inputs are dynamically changeable while the simulation is running. The fixed configuration can be entered either using a register-based approach or a graphical user interface, while the dynamic values supplied at the inputs must correspond to raw register values. The figure below shows the block and its parameters for the register-based version.

pict   [Picture]
Register based ePWM module model

As depicted above, the block can be configured directly using the registers of the hardware module, making it possible to exactly mirror the configuration applied to the target. Also as shown, either hexadecimal, decimal or binary representation can be used to enter the configuration.

Supported Submodules and Functionalities

The ePWM type 0/1 module consists of several submodules:

[Picture]
Submodules of the ePWM type 1 module [1]

The PLECS ePWM model accurately reflects the most relevant features of the following submodules:

Time-Base (TB) Submodule

This submodule realizes a counter that can operate in three different modes for the generation of asymmetrical and symmetrical PWM signals. The three modes, up-count, down-count, and up-down-count, are visualized below.

[Picture]
Counter modes and resulting PWM frequencies [1]

In up-count mode, the counter is incremented from 0   to a counter period TBPRD using a counter clock with period TTBCLK  . When the counter reaches the period, the subsequent count value is reset to zero and the sequence is repeated. When the counter is equal to zero or the period value, the submodule produces a pulse of one counter clock period, which, together with the actual counter direction, is sent to the subsequent Action Qualifier submodule.

The period of the timer clock can be calculated based on the system clock (SYSCLKOUT) and the two clock dividers (CLKDIV and HSPCLKDIV ) by:

T       = CLKDIV--⋅HSPCLKDIV----
 TBCLK        SYSCLKOUT

The resulting PWM period further depends on the counting mode, the counter period (TBPRD) and the counter clock period as depicted in the figure above.

While the system clock and the period counter value are separately defined in the mask parameters, the counter mode and the clock divider are jointly configured in the TBCTL register.

pict
TBCTL Register Configuration [1]

The CLKDIV and HSPCLKDIV cells select the desired clock dividers and the CTRMODE cell defines the counter mode. Only counter modes 00, 01, and 10 are supported by the PLECS ePWM model.

Example Configuration - Step 1

This example is based on the parameter mask shown at the beginning of this chapter and will be further developed in subsequent sections. The TBCTL register is configured to:

TBCTL  = 1024  ^=  0 0 0 0 0 1    0 0    0 0 0 0 0 0 0 0
                       C◟L◝K◜DI◞V HSP◟C◝L◜◞KDIV          CT◟R◝M◜O◞DE

According to this configuration, the time base submodule is operating in the up-count mode with a timer clock period twice the system-clock period. The resulting PWM signal has the following period:

T     = (TBPRD  + 1) ⋅ CLKDIV-⋅HSPCLKDIV----= 187.525 μs.
  PWM                     SYSCLKOUT

Counter-Compare (CC) Submodule

This submodule is responsible for generating the pulses CTR = CMPA and CTR = CMPB used by the Action-Qualifier submodule. In a typical application, the compare values change continuously during operation and therefore need to be part of the dynamic configuration (block inputs). The PLECS implementation only supports the shadow mode for the CMPx registers, i.e. the content of a CMPx register is only transferred to the internal configuration at reload events. The reload events are specified in the CMPCTL register.

pict
CMPCTL Register Configuration [1]

For efficiency, the PLECS ePWM model only supports the following combinations of counter mode and reload events:

CTRMODELOADAMODELOADBMODE
Up-countCTR = 0CTR = 0
Down-countCTR = PRDCTR = PRD
Up-down-count CTR = 0
or
CTR = 0 or CTR = PRD
CTR = 0
or
CTR = 0 or CTR = PRD

Furthermore, only coinciding configurations for LOADAMODE and LOADBMODE are supported.

In the example configuration, the CMPCTL register needs to be set to 0   because the counter is operating in up-count mode.

Action-Qualifier (AQ) Submodule

This submodule sets the EPWMx outputs based on the flags generated by the Time-Base and Counter-Compare submodules. The AQCTLx registers configure the actions to be performed at the different events. Similiar to the CMPx registers, the AQCTLx registers are operated in shadow mode and are reloaded at both the zero and the period event.

[Picture]
ePWM timing example [1]

The figure above shows an example (Case 2) where the ePWM output is set to high at the CTR = CMPA event. As depicted, an output change always lags the event by one counter clock period. The following shows the structure of the AQCTL register.

pict
AQCTL Register Configuration [1]

Actions depend on the counter direction. For example, the register cell CBD defines what happens to the corresponding ePWMx output when the counter equals CMPB, when the counter is counting down. The following configurations exist:

If events occur simultaneously, the ePWM module respects a priority assignment based on the counter mode. The following figures show the Action-Qualifier prioritization.

[Picture]
Action-Qualifier prioritization in up-down-count mode [1]

[Picture]
Action-Qualifier prioritization in up-count mode [1]

[Picture]
Action-Qualifier prioritization in down-count mode [1]

Notice how software-forced events have the highest priority in all three count modes. Software forcing is configured by the Action-Qualifier-Continous-Software-Force-Register (AQCSFRC), provided as an input to the PLECS block to allow dynamic register configuration.

pict
AQCSFRC Register Configuration [1]

The figure above shows the relevant cells of the register where CSFA and CSFB can be used to force an output. The following configurations are supported:

As illustrated in the previous ePWM timing example, the change of an ePWMx output lags the change of AQCSFRC by one counter clock period. Similar to the previously described registers with dynamic configuration, the AQCSFRC register is operated in shadow mode. The reload events can be defined with the AQSFRC register.

pict
AQSFRC Register Configuration [1]

The supported modes for RLDCSF are listed below.

Immediate mode for loading is not supported due to implementation efficiency reasons.

Example Configuration - Step 2

The following figure shows an example using the actions defined by the AQCTL registers. Refer to [1] for a detailed explanation of the action symbols.

[Picture]
Desired ePWMA and ePWMB output signals [1]

To realize the above ePWM signals, the dynamic configuration must be set as follows:

CMPA  = 3500,CMPB  = 2000,AQCSFRC   = 0

Furthermore, the Action-Qualifier must be set as shown below:

AQCTLA   = 18   ^=  0 0 0 0 ◟0◝ 0◜◞0◟◝0◜◞ 0◟◝0◜◞ 0◟◝◜1◞ 0◟◝◜0◞◟1◝ 0◜◞
                          CBD CBU  CAD CAU  PRDZRO

AQCTLB   = 258  ^=  0 0 0 0 ◟0◝ 0◜◞0◟◝1◜◞ 0◟◝0◜◞ 0◟◝◜0◞ 0◟◝◜0◞◟1◝ 0◜◞
                          CBD CBU  CAD CAU  PRDZRO

Event-Trigger (ET) Submodule

This submodule utilizes the signals generated by the Time Base and Counter Compare submodules to generate events (pulses) at the ePWMSOCx outputs. Such pulses can trigger an ADC conversion or invoke the execution of a control algorithm or PIL block. For each ePWMSOC channel, the Event Trigger module provides an internal 2-bit counter which permits a downsampling of events. The following diagram shows the internal structure for the example of SOCA.

[Picture]
Event Trigger Logic [1]

As can be seen, the counter is being incremented using one of the source signals on the right-hand side. The incrementing source signal is selected by the SOCxSEL field. An SOC pulse is generated when the SOCxCNT reaches its configurable period (SOCxPRD) and pulse generation is activated by the SOCx flag. The configuration for both the SOCA and SOCB portion of the Event Trigger is set by the registers ETSEL and ETPS, which are realized as static parameters of the PLECS model.

The ETSEL register has the following structure.

pict
ETSEL Register Configuration [1]

The SOCxEN bits activate or deactivate the SOCx pulses. The SOCxSEL cells determine the source for the event trigger counter. Note, SOCxSEL   = 000   is not supported in the model.

This figure shows the structure of the ETPS register.

pict
ETPS Register Configuration [1]

The SOCxCNT cells allow initialization of the event counter. The SOCxPRD bits determine the number of events that must occur before an SOCx pulse is generated. Refer to [1] for detailed information regarding the configuration of the ETPS register.

Example Configuration - Step 3

A possible use case for the Event-Trigger submodule is to generate a SOCA pulse every second time the TB-counter meets the CMPA value. To achieve this behavior, the ET is configured as follows.

ETSEL  = 0xC00    ^=  0 0 0 0  1     1-0 0    0 0 0 0 0 0 0 0
                           SO◟C◝A◜E◞N SO◟C◝A◜S◞EL

This setting enables the SOCA pulses and uses the CTR = CMPA event for incrementing the ET-counter. Note that SOCB pulses are completely disabled in this example.

ETPS   = 512   ^=  0 0 0 0   0 0     1 0    0 0 0 0 0 0 0 0
                         SO◟C◝A◜C◞NT SO◟C◝A◜P◞RD

Dead-Band Submodule

The role of this submodule is to add programmable delays to rising and falling edges of the ePWM signals and to generate signal pairs with configurable polarity. The figure below depicts the internal structure of the Dead-Band submodule.

[Picture]
Dead-Band Logic [1]

As shown, the PWMx signals from the Action-Qualifier submodule are post-processed based on the DBCTL register settings. Furthermore, the delay times are programmables by the registers DBRED and DBFED for the rising and falling edge delay, respectively. The structure of the DBCTL register is shown in the following block diagram.

pict
DBCTL Register Configuration [1]

The submodule register cells allow for the following settings:

Refer to [1] for detailed information regarding the configuration of the DBCTL register.

Example Configuration - Step 4

In the sample configuration, the signal EPWMB is selected as the source for both delay counters. Further, both the rising and falling edge of the outputs are delayed by 10 counter clock periods and the polarities are not inverted. The DBCTL register therefore should be configured as follows.

DBCTL  = 0b110011 ^=  0 0 0 0 0 0 0 0 0 0 1◟◝1◜◞ 0◟◝0◜◞      1◟◝ 1◜◞
                                    INxMODE  POLxSELOUTxMODE

With the HALFCYCLE bit set to zero, the DBRED and DBFED must be configured to:

DBRED  = 10 , DBFED   = 10

Analog Digital Converter (ADC) Type 3

The PLECS peripheral library provides two blocks for the TI ADC type 3 module, one with a register based configuration mask and a second with a graphical user interface. The figure below shows the appearance of the register-based version.

pict
Register-based ADC module model

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.

Both ADC blocks interface with other PLECS components over the following terminal groups.

ADC Module Overview

The PLECS ADC model implements the most relevant features of the MCU peripheral.

[Picture]
Overview of the type 3 ADC module [1]

The ADC model implements these logical submodules:

ADC Converter with result registers

The type 3 ADC module contains a single 12-bit converter. Either an internal or an external voltage reference can be selected.

The converter takes 13   ADC clocks for a single conversion. The period of an ADC clock, and therefore the time base for the module, is determined based on the system clock and the two clock dividers specified in the ADCCTL2 register.

pict
ADCCTL2 Register structure [1]

By using the bits CLKDIV4EN and CLKDIV2EN the ADC time base can be specified as follows.

CLKDIV2ENCLKDIV4ENADC clock
00SYSCLK
01SYSCLK
10SYSCLK / 2
11SYSCLK / 4

The bit ADCNONOVERLAP determines if an overlap of sampling and conversion is allowed in case of multiple pending conversion requests.

Once a conversion has completed, the result is stored to one of the 16 result registers ADCRESULT0 - ADCRESULT15. These are directly associated with the SOC. The content of the result registers is available at the output ports of the model. The representation of the conversion result can be chosen with the mask parameter Output Mode.

ADC Reference Voltage Generator

The ADC can use an internal or an external reference voltage. The internal bandgap range is [0V...3.3V], while the external reference can be specified in the component mask.

pict
ADCCTL1 Register structure [1]

With the bit ADCREFSEL, the desired voltage reference can be chosen.

The component only supports the late interrupt pulse mode. Therefore the bit INTPULSEPOS should be one.

ADC Sample Generation Logic

The ADC Sample Generation Logic responds to the SOCx signals, which are based on 16 individual sets of configuration parameters SOC0 - SOC15. Every SOC contains the following information:

The register used for configuring a SOC is shown below.

pict
ADCSOCxCTL Register structure [1]

The register cell ACQPS defines the length of the sampling window. The minimum value valid is 06h   which sets the Sample Window to 6+1 ADC clock cycles. Note according to the hardware documentation, there are a number of invalid settings for this register field:

10 , 11 , 12 , 13 , 14 , 1D , 1E , 1F , 20 , 21 , 2A , 2B  , 2C
  h    h    h   h    h     h    h    h    h   h     h    h    h

2Dh , 2Eh , 37h , 38h , 39h , 3Ah , 3Bh

The time needed for a full conversion can be calculated with the following equation.

Tconv = (ACQPS + 1)⋅ADCclk + 13⋅ADC  clk
      ◟--------◝◜--------◞  ◟---◝◜---◞
          SamplingWindow       Conversion

The CHSEL field associates an input pin with a specific SOC. The component allows single and simultaneous sampling - see section ADC Input Circuit. For an SOC in single sample mode, cell configuration is as follows.

CHSELInput
0hADCINA0
1hADCINA1
......
7hADCINA7
8hADCINB0
......
FhADCINB7

In case of simultaneous sample mode, the channel selection is configured as pairs.

CHSELInput pair
0hADCINA0 / ADCINB0
1hADCINA1 / ADCINB1
......
7hADCINA7 / ADCINB7
> 7hInvalid Selection

With the TRIGSEL field it is possible to choose a particular trigger source available as a block input. The PLECS component only supports ePWMx_SOCy trigger signals. The following table shows the mapping to the hexadecimal representation. Configurations above 14
  h   and below 05
  h   are invalid and result in an error.

TRIGSELInput / Source
05hePWM1_SOCA
06hePWM1_SOCB
07hePWM2_SOCA
......
14hePWM8_SOCB

Additionally, it is possible to configure the interrupt signals INT1 and INT2 to trigger ADC conversions. See section ADC Interrupt Logic for further details.

During operation of an ADC, more than one conversion trigger can occur simultaneously. An SOC can also be triggered while a conversion is already active. A round robin method prioritizes pending SOCs. This scheme is accurately reflected by the PLECS component. The figure below shows an example snapshot of the round robin wheel.

[Picture]
ADC Prioritization example [1]

This wheel consist of 16 SOC flags and a round robin pointer (RRPOINTER). An SOC flag is set when a trigger is received and is cleared when the corresponding conversion finishes. The round robin pointer always points to the last converted SOC and is changed with the end of every conversion. In the PLECS ADC model, the round robin pointer initially points to SOC15. In the example above, the round robin pointer points to SOC7 indicating this is the last converted SOC. At this point in time, the SOC2 and SOC12 are triggered and the corresponding flags are set. For prioritization, the ADC starts with RRPOINTER+1 and goes clockwise through the round robin wheel, meaning SOC12 is executed next in this example.

The hardware ADC also provides higher prioritized SOCs and a ONESHOT single conversion mode. These are not supported by the PLECS model.

ADC Input Circuit

The Input Circuit of the type 3 ADC module consists of two separate Sample&Hold circuits (S&H), each connected to a multiplexer. The field CHSEL from the ADCSOCxCTL register associates an input with a particular SOC. Measurements of TEMP SENSOR and VREFLO are not supported by the PLECS model. The figure below shows the hardware circuit schematic of an ADCIN voltage connected to an S&H circuit.

[Picture]
ADCInx Input Model [1]

After an SOC is triggered from the round robin wheel, the switch is closed for the sampling window changing the voltage of the sampling Capacitor Ch  . Once the sampling time has elapsed, the switch is opened and the conversion starts. For simulation efficiency reasons, the PLECS model of the ADC approximates this behavior by taking the average of the input values at the begin and end of the sampling window.

The type 3 ADC further provides single as well as simultaneous measurements. For a single measurement, only one S&H circuit is active at a time. For simultaneous measurements, both S&H circuits operate in parallel, sampling two different voltages at the same time. The conversion is carried out sequentially starting with the upper S&H voltage. The sampling mode is assigned pairwise, always in groups of even and odd SOCs using the register shown below.

pict
ADCSAMPLEMODE Register structure [1]

With the bit SIMULENx, the sampling mode can be chosen as follows.

In case of simultaneous mode, both SOCs can still be configured independently by the ADCSOCxCTL registers. The behavior during conversion (sample window length and channel selection) is always determined by the triggered SOC. For a more advanced understanding of the modules behavior and configuration, please refer to [1].

ADC Interrupt Logic

For every conversion, the ADC sample generation logic generates an end of conversion pulse (EOC) with duration one ADC clock period. This pulse is generated one cycle before latching the conversion result. The interrupt pulse always lags the EOC pulse by one ADC clock period and therefore is simultaneous to the result latch. The ADC Interrupt Logic can generate the interrupts ADCINT1-ADCINT9, which are available at the output ports of the ADC model. With the register below, the interrupt behavior can be configured.

pict
INTSELxNy Register structure for the example of INT1 and INT2 [1]

The INTxE bit enables the interrupt generation by an EOC flag.

The INTxSEL cell defines which EOC flag triggers the interrupt.

INTxSELInterrupt Trigger
00hEOC0 triggers interrupt ADCINTx
01hEOC1 triggers interrupt ADCINTx
......
0fhEOC15 triggers interrupt ADCINTx
> 0fhInvalid Selection


Note  The cells INT10E and INT10SEL in INTSEL9N10 have no effect because the model only supports the interrupts ADCINT1-ADCINT9.
Additionally, the interrupts INT1 and INT2 can be configured to internally trigger SOCs, using the the following registers:

pict
ADCINTSOCSEL1 Register structure [1]

pict
ADCINTSOCSEL2 Register structure [1]

The field SOCx can be configured as follows.

SOCxInterrupt Trigger
00No ADCINT will trigger SOCx
01ADCINT1 will trigger SOCx
10ADCINT2 will trigger SOCx
11Invalid Selection

The setting in this register, if not 00  , overwrites the trigger setting defined in the field TRIGSEL of the ADCSOCCTLx register.

Reference

Texas Instruments: TMS320x2806x Piccolo Technical Reference Manual, Literature Number SPRUH18D, January 2011-February 2013