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Plant Code Generation: Thyristor Converter 6-Pulse, 3-Phase

Overview

This example demonstrates PLECS Standalone code generation capabilities for a three-phase thyristor (SCR) rectifier. Please note that in order to follow the steps as described below and run the simulation, you will need a PLECS Standalone Coder license to enable code generation. To request a trial license for the PLECS Coder, please email Plexim at info@plexim.com.

An explanation of the 6-pulse, 3-phase thyristor converter is given in the demo model Thyristor Converter 6-Pulse, 3-Phase.

Simulation

Important: Create a working copy of this model (File → Save as...) before making changes or attempting to generate code.

The DC-side reference current is initially set to zero. At t=10 ms, the reference current is ramped up to 10 A, and subsequently stepped to 25 A at t=60 ms. Run the simulation and observe the DC current waveform in the Scope. Notice that the current contains a low-frequency AC-component. Save the completed simulation trace and label it as "Normal Mode".

Next, we will generate ANSI-C code for the plant using the code generation capabilities of PLECS. Navigate to the subsystem settings of the electrical circuit contained in the subsystem labeled "Circuit" and choose Subsystem → Execution settings... from the Edit menu or the context menu (by right-clicking on the block). Check the option Enable code generation (remember that this option is only shown if you have a license for the PLECS Standalone Coder). This will automatically enable the Treat as atomic unit option. To allow code generation, the electrical circuit must be treated as an atomic unit. Click on Apply and notice how the border of the subsystem is drawn with a thicker line to indicate the "atomic" configuration.

Checking the option Enable code generation also enables the Code Generation tab, which is used to configure the Coder. In order to generate C code for a continuous system, its equations must be discretized. The parameter Discretization step size specifies the sample time for the discretization. The Code Generation tab includes several other Coder options and configurations. For example, the output directory for the generated code can be changed from its default location. Please refer to the PLECS Documentation for more information.

Begin by discretizing the model with a step size of 1e-3. Then, generate code by clicking the Generate code button. Notice the C files that appear in the specified output directory. Checking the option Enable code generation also enables the Simulation mode option on on the General tab. When this parameter is set to Normal, which is the default, the subsystem is simulated using the contained native PLECS blocks. When the parameter is set to CodeGen, the generated code is automatically compiled by PLECS and executed in place of the subsystem during a simulation. The Simulation mode selection is also conveniently available from the Subsystem menu. This functionality, combined with the Hold current trace feature of the Scope, allows for an effective verification of the behavior of the generated code, by comparing the results against those obtained from a normal simulation.

Select CodeGen as the simulation mode from the drop-down menu and apply the changes. The border of the subsystem is now highlighted with dashed lines to indicate that this portion of the model will execute using the generated code. Rerun the simulation and observe the (large) deviation of the simulation results from the previous run. Clearly, the discretization at 1e-3 is not acceptable. Save the current trace and label it as "CodeGen 1e-3".

Now, modify the step size to 1e-4. Generate the code for this new step size and apply the changes to the model. Rerun the simulation and save the new trace as "CodeGen 1e-4". Notice the improved precision of the results when using the generated code with the reduced step size. Reduce the step size further if desired.

PLECS Standalone produces C code according to an API that permits easy integration with the realtime simulation framework. Navigate to the specified output folder to find one header file and one implementation file. Inspect both files with a text editor. The files are named after the subsystem for which the code was generated ("Circuit") and have extensions .h and .c file, respectively.

For more information on code generation in PLECS Standalone, please consult the PLECS User Manual or the PLECS documentation accessed from the Help menu.