let DMA_Trigger = [
	{ name: "DMA_TRIGGER_SOFTWARE", displayName: "TRIGGER SOFTWARE" },
	{ name: "DMA_TRIGGER_ADCA1", displayName: "TRIGGER ADCA1" },
	{ name: "DMA_TRIGGER_ADCA2", displayName: "TRIGGER ADCA2" },
	{ name: "DMA_TRIGGER_ADCA3", displayName: "TRIGGER ADCA3" },
	{ name: "DMA_TRIGGER_ADCA4", displayName: "TRIGGER ADCA4" },
	{ name: "DMA_TRIGGER_ADCAEVT", displayName: "TRIGGER ADCAEVT" },
	{ name: "DMA_TRIGGER_ADCB1", displayName: "TRIGGER ADCB1" },
	{ name: "DMA_TRIGGER_ADCB2", displayName: "TRIGGER ADCB2" },
	{ name: "DMA_TRIGGER_ADCB3", displayName: "TRIGGER ADCB3" },
	{ name: "DMA_TRIGGER_ADCB4", displayName: "TRIGGER ADCB4" },
	{ name: "DMA_TRIGGER_ADCBEVT", displayName: "TRIGGER ADCBEVT" },
	{ name: "DMA_TRIGGER_ADCC1", displayName: "TRIGGER ADCC1" },
	{ name: "DMA_TRIGGER_ADCC2", displayName: "TRIGGER ADCC2" },
	{ name: "DMA_TRIGGER_ADCC3", displayName: "TRIGGER ADCC3" },
	{ name: "DMA_TRIGGER_ADCC4", displayName: "TRIGGER ADCC4" },
	{ name: "DMA_TRIGGER_ADCCEVT", displayName: "TRIGGER ADCCEVT" },
	{ name: "DMA_TRIGGER_ADCD1", displayName: "TRIGGER ADCD1" },
	{ name: "DMA_TRIGGER_ADCD2", displayName: "TRIGGER ADCD2" },
	{ name: "DMA_TRIGGER_ADCD3", displayName: "TRIGGER ADCD3" },
	{ name: "DMA_TRIGGER_ADCD4", displayName: "TRIGGER ADCD4" },
	{ name: "DMA_TRIGGER_ADCDEVT", displayName: "TRIGGER ADCDEVT" },
	{ name: "DMA_TRIGGER_ADCE1", displayName: "TRIGGER ADCE1" },
	{ name: "DMA_TRIGGER_ADCE2", displayName: "TRIGGER ADCE2" },
	{ name: "DMA_TRIGGER_ADCE3", displayName: "TRIGGER ADCE3" },
	{ name: "DMA_TRIGGER_ADCE4", displayName: "TRIGGER ADCE4" },
	{ name: "DMA_TRIGGER_ADCEEVT", displayName: "TRIGGER ADCEEVT" },
	{ name: "DMA_TRIGGER_CPU1_XINT1", displayName: "TRIGGER CPU1 XINT1" },
	{ name: "DMA_TRIGGER_CPU1_XINT2", displayName: "TRIGGER CPU1 XINT2" },
	{ name: "DMA_TRIGGER_CPU1_XINT3", displayName: "TRIGGER CPU1 XINT3" },
	{ name: "DMA_TRIGGER_CPU1_XINT4", displayName: "TRIGGER CPU1 XINT4" },
	{ name: "DMA_TRIGGER_CPU1_XINT5", displayName: "TRIGGER CPU1 XINT5" },
	{ name: "DMA_TRIGGER_CPU2_XINT1", displayName: "TRIGGER CPU2 XINT1" },
	{ name: "DMA_TRIGGER_CPU2_XINT2", displayName: "TRIGGER CPU2 XINT2" },
	{ name: "DMA_TRIGGER_CPU2_XINT3", displayName: "TRIGGER CPU2 XINT3" },
	{ name: "DMA_TRIGGER_CPU2_XINT4", displayName: "TRIGGER CPU2 XINT4" },
	{ name: "DMA_TRIGGER_CPU2_XINT5", displayName: "TRIGGER CPU2 XINT5" },
	{ name: "DMA_TRIGGER_CPU3_XINT1", displayName: "TRIGGER CPU3 XINT1" },
	{ name: "DMA_TRIGGER_CPU3_XINT2", displayName: "TRIGGER CPU3 XINT2" },
	{ name: "DMA_TRIGGER_CPU3_XINT3", displayName: "TRIGGER CPU3 XINT3" },
	{ name: "DMA_TRIGGER_CPU3_XINT4", displayName: "TRIGGER CPU3 XINT4" },
	{ name: "DMA_TRIGGER_CPU3_XINT5", displayName: "TRIGGER CPU3 XINT5" },
	{ name: "DMA_TRIGGER_EPWM1SOCA", displayName: "TRIGGER EPWM1SOCA" },
	{ name: "DMA_TRIGGER_EPWM1SOCB", displayName: "TRIGGER EPWM1SOCB" },
	{ name: "DMA_TRIGGER_EPWM2SOCA", displayName: "TRIGGER EPWM2SOCA" },
	{ name: "DMA_TRIGGER_EPWM2SOCB", displayName: "TRIGGER EPWM2SOCB" },
	{ name: "DMA_TRIGGER_EPWM3SOCA", displayName: "TRIGGER EPWM3SOCA" },
	{ name: "DMA_TRIGGER_EPWM3SOCB", displayName: "TRIGGER EPWM3SOCB" },
	{ name: "DMA_TRIGGER_EPWM4SOCA", displayName: "TRIGGER EPWM4SOCA" },
	{ name: "DMA_TRIGGER_EPWM4SOCB", displayName: "TRIGGER EPWM4SOCB" },
	{ name: "DMA_TRIGGER_EPWM5SOCA", displayName: "TRIGGER EPWM5SOCA" },
	{ name: "DMA_TRIGGER_EPWM5SOCB", displayName: "TRIGGER EPWM5SOCB" },
	{ name: "DMA_TRIGGER_EPWM6SOCA", displayName: "TRIGGER EPWM6SOCA" },
	{ name: "DMA_TRIGGER_EPWM6SOCB", displayName: "TRIGGER EPWM6SOCB" },
	{ name: "DMA_TRIGGER_EPWM7SOCA", displayName: "TRIGGER EPWM7SOCA" },
	{ name: "DMA_TRIGGER_EPWM7SOCB", displayName: "TRIGGER EPWM7SOCB" },
	{ name: "DMA_TRIGGER_EPWM8SOCA", displayName: "TRIGGER EPWM8SOCA" },
	{ name: "DMA_TRIGGER_EPWM8SOCB", displayName: "TRIGGER EPWM8SOCB" },
	{ name: "DMA_TRIGGER_EPWM9SOCA", displayName: "TRIGGER EPWM9SOCA" },
	{ name: "DMA_TRIGGER_EPWM9SOCB", displayName: "TRIGGER EPWM9SOCB" },
	{ name: "DMA_TRIGGER_EPWM10SOCA", displayName: "TRIGGER EPWM10SOCA" },
	{ name: "DMA_TRIGGER_EPWM10SOCB", displayName: "TRIGGER EPWM10SOCB" },
	{ name: "DMA_TRIGGER_EPWM11SOCA", displayName: "TRIGGER EPWM11SOCA" },
	{ name: "DMA_TRIGGER_EPWM11SOCB", displayName: "TRIGGER EPWM11SOCB" },
	{ name: "DMA_TRIGGER_EPWM12SOCA", displayName: "TRIGGER EPWM12SOCA" },
	{ name: "DMA_TRIGGER_EPWM12SOCB", displayName: "TRIGGER EPWM12SOCB" },
	{ name: "DMA_TRIGGER_EPWM13SOCA", displayName: "TRIGGER EPWM13SOCA" },
	{ name: "DMA_TRIGGER_EPWM13SOCB", displayName: "TRIGGER EPWM13SOCB" },
	{ name: "DMA_TRIGGER_EPWM14SOCA", displayName: "TRIGGER EPWM14SOCA" },
	{ name: "DMA_TRIGGER_EPWM14SOCB", displayName: "TRIGGER EPWM14SOCB" },
	{ name: "DMA_TRIGGER_EPWM15SOCA", displayName: "TRIGGER EPWM15SOCA" },
	{ name: "DMA_TRIGGER_EPWM15SOCB", displayName: "TRIGGER EPWM15SOCB" },
	{ name: "DMA_TRIGGER_EPWM16SOCA", displayName: "TRIGGER EPWM16SOCA" },
	{ name: "DMA_TRIGGER_EPWM16SOCB", displayName: "TRIGGER EPWM16SOCB" },
	{ name: "DMA_TRIGGER_EPWM17SOCA", displayName: "TRIGGER EPWM17SOCA" },
	{ name: "DMA_TRIGGER_EPWM17SOCB", displayName: "TRIGGER EPWM17SOCB" },
	{ name: "DMA_TRIGGER_EPWM18SOCA", displayName: "TRIGGER EPWM18SOCA" },
	{ name: "DMA_TRIGGER_EPWM18SOCB", displayName: "TRIGGER EPWM18SOCB" },
	{ name: "DMA_TRIGGER_TINT0", displayName: "TRIGGER TINT0" },
	{ name: "DMA_TRIGGER_TINT1", displayName: "TRIGGER TINT1" },
	{ name: "DMA_TRIGGER_TINT2", displayName: "TRIGGER TINT2" },
	{ name: "DMA_TRIGGER_CPU2_TINT0", displayName: "TRIGGER CPU2 TINT0" },
	{ name: "DMA_TRIGGER_CPU2_TINT1", displayName: "TRIGGER CPU2 TINT1" },
	{ name: "DMA_TRIGGER_CPU2_TINT2", displayName: "TRIGGER CPU2 TINT2" },
	{ name: "DMA_TRIGGER_CPU3_TINT0", displayName: "TRIGGER CPU3 TINT0" },
	{ name: "DMA_TRIGGER_CPU3_TINT1", displayName: "TRIGGER CPU3 TINT1" },
	{ name: "DMA_TRIGGER_CPU3_TINT2", displayName: "TRIGGER CPU3 TINT2" },
	{ name: "DMA_TRIGGER_ECAP1", displayName: "TRIGGER ECAP1" },
	{ name: "DMA_TRIGGER_ECAP2", displayName: "TRIGGER ECAP2" },
	{ name: "DMA_TRIGGER_ECAP3", displayName: "TRIGGER ECAP3" },
	{ name: "DMA_TRIGGER_ECAP4", displayName: "TRIGGER ECAP4" },
	{ name: "DMA_TRIGGER_ECAP5", displayName: "TRIGGER ECAP5" },
	{ name: "DMA_TRIGGER_ECAP6", displayName: "TRIGGER ECAP6" },
	{ name: "DMA_TRIGGER_LINATX", displayName: "TRIGGER LINATX" },
	{ name: "DMA_TRIGGER_LINARX", displayName: "TRIGGER LINARX" },
	{ name: "DMA_TRIGGER_LINBTX", displayName: "TRIGGER LINBTX" },
	{ name: "DMA_TRIGGER_LINBRX", displayName: "TRIGGER LINBRX" },
	{ name: "DMA_TRIGGER_SYNC", displayName: "TRIGGER SYNC" },
	{ name: "DMA_TRIGGER_SPIATX", displayName: "TRIGGER SPIATX" },
	{ name: "DMA_TRIGGER_SPIARX", displayName: "TRIGGER SPIARX" },
	{ name: "DMA_TRIGGER_SPIBTX", displayName: "TRIGGER SPIBTX" },
	{ name: "DMA_TRIGGER_SPIBRX", displayName: "TRIGGER SPIBRX" },
	{ name: "DMA_TRIGGER_SPICTX", displayName: "TRIGGER SPICTX" },
	{ name: "DMA_TRIGGER_SPICRX", displayName: "TRIGGER SPICRX" },
	{ name: "DMA_TRIGGER_SPIDTX", displayName: "TRIGGER SPIDTX" },
	{ name: "DMA_TRIGGER_SPIDRX", displayName: "TRIGGER SPIDRX" },
	{ name: "DMA_TRIGGER_SPIETX", displayName: "TRIGGER SPIETX" },
	{ name: "DMA_TRIGGER_SPIERX", displayName: "TRIGGER SPIERX" },
	{ name: "DMA_TRIGGER_CLB1INT", displayName: "TRIGGER CLB1INT" },
	{ name: "DMA_TRIGGER_CLB2INT", displayName: "TRIGGER CLB2INT" },
	{ name: "DMA_TRIGGER_CLB3INT", displayName: "TRIGGER CLB3INT" },
	{ name: "DMA_TRIGGER_CLB4INT", displayName: "TRIGGER CLB4INT" },
	{ name: "DMA_TRIGGER_CLB5INT", displayName: "TRIGGER CLB5INT" },
	{ name: "DMA_TRIGGER_CLB6INT", displayName: "TRIGGER CLB6INT" },
	{ name: "DMA_TRIGGER_FSITXA", displayName: "TRIGGER FSITXA" },
	{ name: "DMA_TRIGGER_FSIRXA", displayName: "TRIGGER FSIRXA" },
	{ name: "DMA_TRIGGER_FSIA_DATA_TAG_MATCH", displayName: "TRIGGER FSIA DATA TAG MATCH" },
	{ name: "DMA_TRIGGER_FSIA_PING_TAG_MATCH", displayName: "TRIGGER FSIA PING TAG MATCH" },
	{ name: "DMA_TRIGGER_FSITXB", displayName: "TRIGGER FSITXB" },
	{ name: "DMA_TRIGGER_FSIRXB", displayName: "TRIGGER FSIRXB" },
	{ name: "DMA_TRIGGER_FSIB_DATA_TAG_MATCH", displayName: "TRIGGER FSIB DATA TAG MATCH" },
	{ name: "DMA_TRIGGER_FSIB_PING_TAG_MATCH", displayName: "TRIGGER FSIB PING TAG MATCH" },
	{ name: "DMA_TRIGGER_FSITXC", displayName: "TRIGGER FSITXC" },
	{ name: "DMA_TRIGGER_FSIRXC", displayName: "TRIGGER FSIRXC" },
	{ name: "DMA_TRIGGER_FSIC_DATA_TAG_MATCH", displayName: "TRIGGER FSIC DATA TAG MATCH" },
	{ name: "DMA_TRIGGER_FSIC_PING_TAG_MATCH", displayName: "TRIGGER FSIC PING TAG MATCH" },
	{ name: "DMA_TRIGGER_FSITXD", displayName: "TRIGGER FSITXD" },
	{ name: "DMA_TRIGGER_FSIRXD", displayName: "TRIGGER FSIRXD" },
	{ name: "DMA_TRIGGER_FSID_DATA_TAG_MATCH", displayName: "TRIGGER FSID DATA TAG MATCH" },
	{ name: "DMA_TRIGGER_FSID_PING_TAG_MATCH", displayName: "TRIGGER FSID PING TAG MATCH" },
	{ name: "DMA_TRIGGER_CPU1_DLT", displayName: "TRIGGER CPU1 DLT" },
	{ name: "DMA_TRIGGER_CPU2_DLT", displayName: "TRIGGER CPU2 DLT" },
	{ name: "DMA_TRIGGER_CPU3_DLT", displayName: "TRIGGER CPU3 DLT" },
	{ name: "DMA_TRIGGER_UARTARX", displayName: "TRIGGER UARTARX" },
	{ name: "DMA_TRIGGER_UARTATX", displayName: "TRIGGER UARTATX" },
	{ name: "DMA_TRIGGER_UARTBTX", displayName: "TRIGGER UARTBTX" },
	{ name: "DMA_TRIGGER_UARTBRX", displayName: "TRIGGER UARTBRX" },
	{ name: "DMA_TRIGGER_UARTCTX", displayName: "TRIGGER UARTCTX" },
	{ name: "DMA_TRIGGER_UARTCRX", displayName: "TRIGGER UARTCRX" },
	{ name: "DMA_TRIGGER_UARTDTX", displayName: "TRIGGER UARTDTX" },
	{ name: "DMA_TRIGGER_UARTDRX", displayName: "TRIGGER UARTDRX" },
	{ name: "DMA_TRIGGER_UARTETX", displayName: "TRIGGER UARTETX" },
	{ name: "DMA_TRIGGER_UARTERX", displayName: "TRIGGER UARTERX" },
	{ name: "DMA_TRIGGER_UARTFTX", displayName: "TRIGGER UARTFTX" },
	{ name: "DMA_TRIGGER_UARTFRX", displayName: "TRIGGER UARTFRX" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_S_CTXIN_REQ", displayName: "TRIGGER DTHE SHA DMA S CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_S_DATAIN_REQ", displayName: "TRIGGER DTHE SHA DMA S DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_S_CTXOUT_REQ", displayName: "TRIGGER DTHE SHA DMA S CTXOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_P_CTXIN_REQ", displayName: "TRIGGER DTHE SHA DMA P CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_P_DATAIN_REQ", displayName: "TRIGGER DTHE SHA DMA P DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SHA_DMA_P_CTXOUT_REQ", displayName: "TRIGGER DTHE SHA DMA P CTXOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_S_CTXIN_REQ", displayName: "TRIGGER DTHE AES DMA S CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_S_DATAIN_REQ", displayName: "TRIGGER DTHE AES DMA S DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_S_DATAOUT_REQ", displayName: "TRIGGER DTHE AES DMA S DATAOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_S_CTXOUT_REQ", displayName: "TRIGGER DTHE AES DMA S CTXOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_P_CTXIN_REQ", displayName: "TRIGGER DTHE AES DMA P CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_P_DATAIN_REQ", displayName: "TRIGGER DTHE AES DMA P DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_P_DATAOUT_REQ", displayName: "TRIGGER DTHE AES DMA P DATAOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_AES_DMA_P_CTXOUT_REQ", displayName: "TRIGGER DTHE AES DMA P CTXOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM3_CTXIN_REQ", displayName: "TRIGGER DTHE SM3 CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM3_DATAIN_REQ", displayName: "TRIGGER DTHE SM3 DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM3_CTXOUT_REQ", displayName: "TRIGGER DTHE SM3 CTXOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM4_CTXIN_REQ", displayName: "TRIGGER DTHE SM4 CTXIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM4_DATAIN_REQ", displayName: "TRIGGER DTHE SM4 DATAIN REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM4_DATAOUT_REQ", displayName: "TRIGGER DTHE SM4 DATAOUT REQ" },
	{ name: "DMA_TRIGGER_DTHE_SM4_CTXOUT_REQ", displayName: "TRIGGER DTHE SM4 CTXOUT REQ" },
	{ name: "DMA_TRIGGER_EPG", displayName: "TRIGGER EPG" },
	{ name: "DMA_TRIGGER_SDFM1FLT1", displayName: "TRIGGER SDFM1FLT1" },
	{ name: "DMA_TRIGGER_SDFM1FLT2", displayName: "TRIGGER SDFM1FLT2" },
	{ name: "DMA_TRIGGER_SDFM1FLT3", displayName: "TRIGGER SDFM1FLT3" },
	{ name: "DMA_TRIGGER_SDFM1FLT4", displayName: "TRIGGER SDFM1FLT4" },
	{ name: "DMA_TRIGGER_SDFM2FLT1", displayName: "TRIGGER SDFM2FLT1" },
	{ name: "DMA_TRIGGER_SDFM2FLT2", displayName: "TRIGGER SDFM2FLT2" },
	{ name: "DMA_TRIGGER_SDFM2FLT3", displayName: "TRIGGER SDFM2FLT3" },
	{ name: "DMA_TRIGGER_SDFM2FLT4", displayName: "TRIGGER SDFM2FLT4" },
	{ name: "DMA_TRIGGER_SDFM3FLT1", displayName: "TRIGGER SDFM3FLT1" },
	{ name: "DMA_TRIGGER_SDFM3FLT2", displayName: "TRIGGER SDFM3FLT2" },
	{ name: "DMA_TRIGGER_SDFM3FLT3", displayName: "TRIGGER SDFM3FLT3" },
	{ name: "DMA_TRIGGER_SDFM3FLT4", displayName: "TRIGGER SDFM3FLT4" },
	{ name: "DMA_TRIGGER_SDFM4FLT1", displayName: "TRIGGER SDFM4FLT1" },
	{ name: "DMA_TRIGGER_SDFM4FLT2", displayName: "TRIGGER SDFM4FLT2" },
	{ name: "DMA_TRIGGER_SDFM4FLT3", displayName: "TRIGGER SDFM4FLT3" },
	{ name: "DMA_TRIGGER_SDFM4FLT4", displayName: "TRIGGER SDFM4FLT4" },
	{ name: "DMA_TRIGGER_SENT1", displayName: "TRIGGER SENT1" },
	{ name: "DMA_TRIGGER_SENT2", displayName: "TRIGGER SENT2" },
	{ name: "DMA_TRIGGER_SENT3", displayName: "TRIGGER SENT3" },
	{ name: "DMA_TRIGGER_SENT4", displayName: "TRIGGER SENT4" },
	{ name: "DMA_TRIGGER_SENT5", displayName: "TRIGGER SENT5" },
	{ name: "DMA_TRIGGER_SENT6", displayName: "TRIGGER SENT6" },
	{ name: "DMA_TRIGGER_WADI1", displayName: "TRIGGER WADI1" },
	{ name: "DMA_TRIGGER_WADI2", displayName: "TRIGGER WADI2" },
	{ name: "DMA_TRIGGER_RTDMA_CH1INT", displayName: "TRIGGER RTDMA CH1INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH2INT", displayName: "TRIGGER RTDMA CH2INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH3INT", displayName: "TRIGGER RTDMA CH3INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH4INT", displayName: "TRIGGER RTDMA CH4INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH5INT", displayName: "TRIGGER RTDMA CH5INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH6INT", displayName: "TRIGGER RTDMA CH6INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH7INT", displayName: "TRIGGER RTDMA CH7INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH8INT", displayName: "TRIGGER RTDMA CH8INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH9INT", displayName: "TRIGGER RTDMA CH9INT" },
	{ name: "DMA_TRIGGER_RTDMA_CH10INT", displayName: "TRIGGER RTDMA CH10INT" },
]
let DMA_MPURegion = [
	{ name: "DMA_MPUR1", displayName: "MPUR1" },
	{ name: "DMA_MPUR2", displayName: "MPUR2" },
	{ name: "DMA_MPUR3", displayName: "MPUR3" },
	{ name: "DMA_MPUR4", displayName: "MPUR4" },
	{ name: "DMA_MPUR5", displayName: "MPUR5" },
	{ name: "DMA_MPUR6", displayName: "MPUR6" },
	{ name: "DMA_MPUR7", displayName: "MPUR7" },
	{ name: "DMA_MPUR8", displayName: "MPUR8" },
	{ name: "DMA_MPUR9", displayName: "MPUR9" },
	{ name: "DMA_MPUR10", displayName: "MPUR10" },
	{ name: "DMA_MPUR11", displayName: "MPUR11" },
	{ name: "DMA_MPUR12", displayName: "MPUR12" },
	{ name: "DMA_MPUR13", displayName: "MPUR13" },
	{ name: "DMA_MPUR14", displayName: "MPUR14" },
	{ name: "DMA_MPUR15", displayName: "MPUR15" },
	{ name: "DMA_MPUR16", displayName: "MPUR16" },
]
let DMA_Channel = [
	{ name: "DMA_CH1", displayName: "CH1" },
	{ name: "DMA_CH2", displayName: "CH2" },
	{ name: "DMA_CH3", displayName: "CH3" },
	{ name: "DMA_CH4", displayName: "CH4" },
	{ name: "DMA_CH5", displayName: "CH5" },
	{ name: "DMA_CH6", displayName: "CH6" },
	{ name: "DMA_CH7", displayName: "CH7" },
	{ name: "DMA_CH8", displayName: "CH8" },
	{ name: "DMA_CH9", displayName: "CH9" },
	{ name: "DMA_CH10", displayName: "CH10" },
]
let DMA_ChannelPriority = [
	{ name: "DMA_CHPRIORITY0", displayName: "DMA channel has Priority 0." },
	{ name: "DMA_CHPRIORITY1", displayName: "DMA channel has Priority 1." },
	{ name: "DMA_CHPRIORITY2", displayName: "DMA channel has Priority 2." },
	{ name: "DMA_CHPRIORITY3", displayName: "DMA channel has Priority 3." },
]
let DMA_InterruptMode = [
	{ name: "DMA_INT_AT_BEGINNING", displayName: "DMA interrupt is generated at the beginning of a transfer" },
	{ name: "DMA_INT_AT_END", displayName: "DMA interrupt is generated at the end of a transfer" },
]
let DMA_EmulationMode = [
	{ name: "DMA_EMULATION_STOP", displayName: "Transmission stops after current read-write access is completed" },
	{ name: "DMA_EMULATION_FREE_RUN", displayName: "Continue DMA operation regardless of emulation suspend" },
]
let DMA_PriorityMode = [
	{ name: "DMA_PRIORITY_ROUND_ROBIN", displayName: "Transmission stops after current read-write access is completed" },
	{ name: "DMA_PRIORITY_SOFTWARE_CONFIG", displayName: "Continue DMA operation regardless of emulation suspend" },
]
let DMA_BurstSignalingMode = [
	{ name: "DMA_BURST_SIGNALING_DISABLE", displayName: "Burst signaling disabled. Last=First=1 though the burst (FIFOs)" },
	{ name: "DMA_BURST_SIGNALING_ENABLE_NO_INT", displayName: "Burst signaling enabled and can't be interrupted (can use with EMIF)" },
]
let DMA_MPUAccessPermission = [
	{ name: "DMA_MPU_NO_ACCESS", displayName: "DMA has no access to the MPU region." },
	{ name: "DMA_MPU_READ_ACCESS", displayName: "DMA has only read access to the MPU region." },
	{ name: "DMA_MPU_READ_WRITE_ACCESS", displayName: "DMA has both read and write access to the MPU region." },
]
let DMA_TOTAL = [
	{ name: "DMA_TOTAL_MPU", displayName: "Out of 32, only 16 are supported in Veloce" },
	{ name: "DMA_TOTAL_CH", displayName: "10 channels in each DMA instance" },
]
let DMA_CFG_ONESHOT = [
	{ name: "DMA_CFG_ONESHOT_DISABLE", displayName: "Only one burst transfer performed per trigger." },
	{ name: "DMA_CFG_ONESHOT_ENABLE", displayName: "Burst transfers occur without additional event triggers after the first." },
]
let DMA_CFG_CONTINUOUS = [
	{ name: "DMA_CFG_CONTINUOUS_DISABLE", displayName: "DMA channel will be disabled at the end of a transfer." },
	{ name: "DMA_CFG_CONTINUOUS_ENABLE", displayName: "DMA reinitializes when the transfer count is zero and waits for a trigger." },
]
let DMA_CFG_READ_SIZE = [
	{ name: "DMA_CFG_READ_SIZE_8BIT", displayName: "DMA reads 8 bits at a time." },
	{ name: "DMA_CFG_READ_SIZE_16BIT", displayName: "DMA reads 16 bits at a time." },
	{ name: "DMA_CFG_READ_SIZE_32BIT", displayName: "DMA reads 32 bits at a time." },
	{ name: "DMA_CFG_READ_SIZE_64BIT", displayName: "DMA reads 64 bits at a time." },
]
let DMA_CFG_WRT_SIZE = [
	{ name: "DMA_CFG_WRT_SIZE_8BIT", displayName: "DMA writes 8 bits at a time." },
	{ name: "DMA_CFG_WRT_SIZE_16BIT", displayName: "DMA writes 16 bits at a time." },
	{ name: "DMA_CFG_WRT_SIZE_32BIT", displayName: "DMA writes 32 bits at a time." },
	{ name: "DMA_CFG_WRT_SIZE_64BIT", displayName: "DMA writes 64 bits at a time." },
]
let DMA_CFG_SIZE = [
	{ name: "DMA_CFG_SIZE_8BIT", displayName: "SIZE 8BIT" },
	{ name: "DMA_CFG_SIZE_16BIT", displayName: "SIZE 16BIT" },
	{ name: "DMA_CFG_SIZE_32BIT", displayName: "SIZE 32BIT" },
	{ name: "DMA_CFG_SIZE_64BIT", displayName: "SIZE 64BIT" },
]
let DMA_MPU_CH = [
	{ name: "DMA_MPU_CH1_ENABLE", displayName: "Enable DMA Channel 1 for the MPU region." },
	{ name: "DMA_MPU_CH2_ENABLE", displayName: "Enable DMA Channel 2 for the MPU region." },
	{ name: "DMA_MPU_CH3_ENABLE", displayName: "Enable DMA Channel 3 for the MPU region." },
	{ name: "DMA_MPU_CH4_ENABLE", displayName: "Enable DMA Channel 4 for the MPU region." },
	{ name: "DMA_MPU_CH5_ENABLE", displayName: "Enable DMA Channel 5 for the MPU region." },
	{ name: "DMA_MPU_CH6_ENABLE", displayName: "Enable DMA Channel 6 for the MPU region." },
	{ name: "DMA_MPU_CH7_ENABLE", displayName: "Enable DMA Channel 7 for the MPU region." },
	{ name: "DMA_MPU_CH8_ENABLE", displayName: "Enable DMA Channel 8 for the MPU region." },
	{ name: "DMA_MPU_CH9_ENABLE", displayName: "Enable DMA Channel 9 for the MPU region." },
	{ name: "DMA_MPU_CH10_ENABLE", displayName: "Enable DMA Channel 10 for the MPU region." },
]
module.exports = {
	DMA_Trigger: DMA_Trigger,
	DMA_MPURegion: DMA_MPURegion,
	DMA_Channel: DMA_Channel,
	DMA_ChannelPriority: DMA_ChannelPriority,
	DMA_InterruptMode: DMA_InterruptMode,
	DMA_EmulationMode: DMA_EmulationMode,
	DMA_PriorityMode: DMA_PriorityMode,
	DMA_BurstSignalingMode: DMA_BurstSignalingMode,
	DMA_MPUAccessPermission: DMA_MPUAccessPermission,
	DMA_TOTAL: DMA_TOTAL,
	DMA_CFG_ONESHOT: DMA_CFG_ONESHOT,
	DMA_CFG_CONTINUOUS: DMA_CFG_CONTINUOUS,
	DMA_CFG_READ_SIZE: DMA_CFG_READ_SIZE,
	DMA_CFG_WRT_SIZE: DMA_CFG_WRT_SIZE,
	DMA_CFG_SIZE: DMA_CFG_SIZE,
	DMA_MPU_CH: DMA_MPU_CH,
}
