let ESM_EventMap = [
	{ name: "ESM_EVENT_ErrorAggregator_CPU1_HPERR", displayName: "EVENT ErrorAggregator CPU1 HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU2_HPERR", displayName: "EVENT ErrorAggregator CPU2 HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU3_HPERR", displayName: "EVENT ErrorAggregator CPU3 HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU1_INT_HPERR", displayName: "EVENT ErrorAggregator CPU1 INT HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU2_INT_HPERR", displayName: "EVENT ErrorAggregator CPU2 INT HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU3_INT_HPERR", displayName: "EVENT ErrorAggregator CPU3 INT HPERR" },
	{ name: "ESM_EVENT_CLOCKFAIL", displayName: "EVENT CLOCKFAIL" },
	{ name: "ESM_EVENT_DCC1_ERR", displayName: "EVENT DCC1 ERR" },
	{ name: "ESM_EVENT_DCC2_ERR", displayName: "EVENT DCC2 ERR" },
	{ name: "ESM_EVENT_DCC3_ERR", displayName: "EVENT DCC3 ERR" },
	{ name: "ESM_EVENT_SYS_PLL_SLIP", displayName: "EVENT SYS PLL SLIP" },
	{ name: "ESM_EVENT_CPU1RSn", displayName: "EVENT CPU1RSn" },
	{ name: "ESM_EVENT_CPU1WD", displayName: "EVENT CPU1WD" },
	{ name: "ESM_EVENT_CPU1_ERAD_INT", displayName: "EVENT CPU1 ERAD INT" },
	{ name: "ESM_EVENT_CPU1_ERAD_NMI", displayName: "EVENT CPU1 ERAD NMI" },
	{ name: "ESM_EVENT_ESM_CPU1_LOW_PRIORITY_INT", displayName: "EVENT ESM CPU1 LOW PRIORITY INT" },
	{ name: "ESM_EVENT_ESM_CPU1_HIGH_PRIORITY_INT", displayName: "EVENT ESM CPU1 HIGH PRIORITY INT" },
	{ name: "ESM_EVENT_LCM_CPU1SS_LCMPERR", displayName: "EVENT LCM CPU1SS LCMPERR" },
	{ name: "ESM_EVENT_CPU2RSn", displayName: "EVENT CPU2RSn" },
	{ name: "ESM_EVENT_CPU2WD", displayName: "EVENT CPU2WD" },
	{ name: "ESM_EVENT_CPU2_ERAD_INT", displayName: "EVENT CPU2 ERAD INT" },
	{ name: "ESM_EVENT_CPU2_ERAD_NMI", displayName: "EVENT CPU2 ERAD NMI" },
	{ name: "ESM_EVENT_ESM_CPU2_LOW_PRIORITY_INT", displayName: "EVENT ESM CPU2 LOW PRIORITY INT" },
	{ name: "ESM_EVENT_ESM_CPU2_HIGH_PRIORITY_INT", displayName: "EVENT ESM CPU2 HIGH PRIORITY INT" },
	{ name: "ESM_EVENT_CPU3RSn", displayName: "EVENT CPU3RSn" },
	{ name: "ESM_EVENT_CPU3WD", displayName: "EVENT CPU3WD" },
	{ name: "ESM_EVENT_CPU3_ERAD_INT", displayName: "EVENT CPU3 ERAD INT" },
	{ name: "ESM_EVENT_CPU3_ERAD_NMI", displayName: "EVENT CPU3 ERAD NMI" },
	{ name: "ESM_EVENT_ESM_CPU3_LOW_PRIORITY_INT", displayName: "EVENT ESM CPU3 LOW PRIORITY INT" },
	{ name: "ESM_EVENT_ESM_CPU3_HIGH_PRIORITY_INT", displayName: "EVENT ESM CPU3 HIGH PRIORITY INT" },
	{ name: "ESM_EVENT_RTDMA_LCM_CMP_ERR", displayName: "EVENT RTDMA LCM CMP ERR" },
	{ name: "ESM_EVENT_ESM_ERRPIN_MON_EVT", displayName: "EVENT ESM ERRPIN MON EVT" },
	{ name: "ESM_EVENT_ESM_PARITY_ERROR", displayName: "EVENT ESM PARITY ERROR" },
	{ name: "ESM_EVENT_HSM_HEA_INT_LO", displayName: "EVENT HSM HEA INT LO" },
	{ name: "ESM_EVENT_HSM_HEA_INT_HI", displayName: "EVENT HSM HEA INT HI" },
	{ name: "ESM_EVENT_INPUTXBAR63", displayName: "EVENT INPUTXBAR63" },
	{ name: "ESM_EVENT_INPUTXBAR64", displayName: "EVENT INPUTXBAR64" },
	{ name: "ESM_EVENT_EPWMXBAR1", displayName: "EVENT EPWMXBAR1" },
	{ name: "ESM_EVENT_EPWMXBAR2", displayName: "EVENT EPWMXBAR2" },
	{ name: "ESM_EVENT_EPWMXBAR3", displayName: "EVENT EPWMXBAR3" },
	{ name: "ESM_EVENT_EPWMXBAR4", displayName: "EVENT EPWMXBAR4" },
	{ name: "ESM_EVENT_EPWMXBAR5", displayName: "EVENT EPWMXBAR5" },
	{ name: "ESM_EVENT_EPWMXBAR6", displayName: "EVENT EPWMXBAR6" },
	{ name: "ESM_EVENT_EPWMXBAR7", displayName: "EVENT EPWMXBAR7" },
	{ name: "ESM_EVENT_EPWMXBAR8", displayName: "EVENT EPWMXBAR8" },
	{ name: "ESM_EVENT_EPWMXBAR9", displayName: "EVENT EPWMXBAR9" },
	{ name: "ESM_EVENT_EPWMXBAR10", displayName: "EVENT EPWMXBAR10" },
	{ name: "ESM_EVENT_EPWMXBAR11", displayName: "EVENT EPWMXBAR11" },
	{ name: "ESM_EVENT_EPWMXBAR12", displayName: "EVENT EPWMXBAR12" },
	{ name: "ESM_EVENT_EPWMXBAR13", displayName: "EVENT EPWMXBAR13" },
	{ name: "ESM_EVENT_EPWMXBAR14", displayName: "EVENT EPWMXBAR14" },
	{ name: "ESM_EVENT_EPWMXBAR15", displayName: "EVENT EPWMXBAR15" },
	{ name: "ESM_EVENT_EPWMXBAR16", displayName: "EVENT EPWMXBAR16" },
	{ name: "ESM_EVENT_OUTPUTXBAR1", displayName: "EVENT OUTPUTXBAR1" },
	{ name: "ESM_EVENT_OUTPUTXBAR2", displayName: "EVENT OUTPUTXBAR2" },
	{ name: "ESM_EVENT_OUTPUTXBAR3", displayName: "EVENT OUTPUTXBAR3" },
	{ name: "ESM_EVENT_OUTPUTXBAR4", displayName: "EVENT OUTPUTXBAR4" },
	{ name: "ESM_EVENT_OUTPUTXBAR5", displayName: "EVENT OUTPUTXBAR5" },
	{ name: "ESM_EVENT_OUTPUTXBAR6", displayName: "EVENT OUTPUTXBAR6" },
	{ name: "ESM_EVENT_OUTPUTXBAR7", displayName: "EVENT OUTPUTXBAR7" },
	{ name: "ESM_EVENT_OUTPUTXBAR8", displayName: "EVENT OUTPUTXBAR8" },
	{ name: "ESM_EVENT_OUTPUTXBAR9", displayName: "EVENT OUTPUTXBAR9" },
	{ name: "ESM_EVENT_OUTPUTXBAR10", displayName: "EVENT OUTPUTXBAR10" },
	{ name: "ESM_EVENT_OUTPUTXBAR11", displayName: "EVENT OUTPUTXBAR11" },
	{ name: "ESM_EVENT_OUTPUTXBAR12", displayName: "EVENT OUTPUTXBAR12" },
	{ name: "ESM_EVENT_OUTPUTXBAR13", displayName: "EVENT OUTPUTXBAR13" },
	{ name: "ESM_EVENT_OUTPUTXBAR14", displayName: "EVENT OUTPUTXBAR14" },
	{ name: "ESM_EVENT_OUTPUTXBAR15", displayName: "EVENT OUTPUTXBAR15" },
	{ name: "ESM_EVENT_OUTPUTXBAR16", displayName: "EVENT OUTPUTXBAR16" },
	{ name: "ESM_EVENT_WADI1_INTN_O", displayName: "EVENT WADI1 INTN O" },
	{ name: "ESM_EVENT_WADI2_INTN_O", displayName: "EVENT WADI2 INTN O" },
	{ name: "ESM_EVENT_CLB1_NMI", displayName: "EVENT CLB1 NMI" },
	{ name: "ESM_EVENT_CLB2_NMI", displayName: "EVENT CLB2 NMI" },
	{ name: "ESM_EVENT_CLB3_NMI", displayName: "EVENT CLB3 NMI" },
	{ name: "ESM_EVENT_CLB4_NMI", displayName: "EVENT CLB4 NMI" },
	{ name: "ESM_EVENT_CLB5_NMI", displayName: "EVENT CLB5 NMI" },
	{ name: "ESM_EVENT_CLB6_NMI", displayName: "EVENT CLB6 NMI" },
	{ name: "ESM_EVENT_EPG_INT", displayName: "EVENT EPG INT" },
	{ name: "ESM_EVENT_ECAT_NMIn", displayName: "EVENT ECAT NMIn" },
	{ name: "ESM_EVENT_MCANA_ECC_CORR_PLS", displayName: "EVENT MCANA ECC CORR PLS" },
	{ name: "ESM_EVENT_MCANA_ECC_UNCORR_TS_PLS", displayName: "EVENT MCANA ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_MCANB_ECC_CORR_PLS", displayName: "EVENT MCANB ECC CORR PLS" },
	{ name: "ESM_EVENT_MCANB_ECC_UNCORR_TS_PLS", displayName: "EVENT MCANB ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_MCANC_ECC_CORR_PLS", displayName: "EVENT MCANC ECC CORR PLS" },
	{ name: "ESM_EVENT_MCANC_ECC_UNCORR_TS_PLS", displayName: "EVENT MCANC ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_MCAND_ECC_CORR_PLS", displayName: "EVENT MCAND ECC CORR PLS" },
	{ name: "ESM_EVENT_MCAND_ECC_UNCORR_TS_PLS", displayName: "EVENT MCAND ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_MCANE_ECC_CORR_PLS", displayName: "EVENT MCANE ECC CORR PLS" },
	{ name: "ESM_EVENT_MCANE_ECC_UNCORR_TS_PLS", displayName: "EVENT MCANE ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_MCANF_ECC_CORR_PLS", displayName: "EVENT MCANF ECC CORR PLS" },
	{ name: "ESM_EVENT_MCANF_ECC_UNCORR_TS_PLS", displayName: "EVENT MCANF ECC UNCORR TS PLS" },
	{ name: "ESM_EVENT_EMIF1_ERR", displayName: "EVENT EMIF1 ERR" },
	{ name: "ESM_EVENT_ADC_SAFETY_CHECK_INT_CPU1", displayName: "EVENT ADC SAFETY CHECK INT CPU1" },
	{ name: "ESM_EVENT_ADC_SAFETY_CHECK_INT_CPU2", displayName: "EVENT ADC SAFETY CHECK INT CPU2" },
	{ name: "ESM_EVENT_ADC_SAFETY_CHECK_INT_CPU3", displayName: "EVENT ADC SAFETY CHECK INT CPU3" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU1_LPERR", displayName: "EVENT ErrorAggregator CPU1 LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU2_LPERR", displayName: "EVENT ErrorAggregator CPU2 LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU3_LPERR", displayName: "EVENT ErrorAggregator CPU3 LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU1_INT_LPERR", displayName: "EVENT ErrorAggregator CPU1 INT LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU2_INT_LPERR", displayName: "EVENT ErrorAggregator CPU2 INT LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_CPU3_INT_LPERR", displayName: "EVENT ErrorAggregator CPU3 INT LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_RTDMA1_HPERR", displayName: "EVENT ErrorAggregator RTDMA1 HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_RTDMA1_LPERR", displayName: "EVENT ErrorAggregator RTDMA1 LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_RTDMA2_HPERR", displayName: "EVENT ErrorAggregator RTDMA2 HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_RTDMA2_LPERR", displayName: "EVENT ErrorAggregator RTDMA2 LPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_SSU_HPERR", displayName: "EVENT ErrorAggregator SSU HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_ECAT_MEM_HPERR", displayName: "EVENT ErrorAggregator ECAT MEM HPERR" },
	{ name: "ESM_EVENT_ErrorAggregator_ECAT_MEM_LPERR", displayName: "EVENT ErrorAggregator ECAT MEM LPERR" },
	{ name: "ESM_EVENT_MCANA_FEVT0", displayName: "EVENT MCANA FEVT0" },
	{ name: "ESM_EVENT_MCANA_FEVT1", displayName: "EVENT MCANA FEVT1" },
	{ name: "ESM_EVENT_MCANA_FEVT2", displayName: "EVENT MCANA FEVT2" },
	{ name: "ESM_EVENT_MCANB_FEVT0", displayName: "EVENT MCANB FEVT0" },
	{ name: "ESM_EVENT_MCANB_FEVT1", displayName: "EVENT MCANB FEVT1" },
	{ name: "ESM_EVENT_MCANB_FEVT2", displayName: "EVENT MCANB FEVT2" },
	{ name: "ESM_EVENT_MCANC_FEVT0", displayName: "EVENT MCANC FEVT0" },
	{ name: "ESM_EVENT_MCANC_FEVT1", displayName: "EVENT MCANC FEVT1" },
	{ name: "ESM_EVENT_MCANC_FEVT2", displayName: "EVENT MCANC FEVT2" },
	{ name: "ESM_EVENT_MCAND_FEVT0", displayName: "EVENT MCAND FEVT0" },
	{ name: "ESM_EVENT_MCAND_FEVT1", displayName: "EVENT MCAND FEVT1" },
	{ name: "ESM_EVENT_MCAND_FEVT2", displayName: "EVENT MCAND FEVT2" },
	{ name: "ESM_EVENT_MCANE_FEVT0", displayName: "EVENT MCANE FEVT0" },
	{ name: "ESM_EVENT_MCANE_FEVT1", displayName: "EVENT MCANE FEVT1" },
	{ name: "ESM_EVENT_MCANE_FEVT2", displayName: "EVENT MCANE FEVT2" },
	{ name: "ESM_EVENT_MCANF_FEVT0", displayName: "EVENT MCANF FEVT0" },
	{ name: "ESM_EVENT_MCANF_FEVT1", displayName: "EVENT MCANF FEVT1" },
	{ name: "ESM_EVENT_MCANF_FEVT2", displayName: "EVENT MCANF FEVT2" },
	{ name: "ESM_EVENT_WADI1_BLOCK1_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI1 BLOCK1 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI1_BLOCK1_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI1 BLOCK1 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI1_BLOCK1_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI1 BLOCK1 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI1_BLOCK2_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI1 BLOCK2 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI1_BLOCK2_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI1 BLOCK2 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI1_BLOCK2_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI1 BLOCK2 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI1_BLOCK3_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI1 BLOCK3 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI1_BLOCK3_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI1 BLOCK3 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI1_BLOCK3_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI1 BLOCK3 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI1_BLOCK4_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI1 BLOCK4 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI1_BLOCK4_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI1 BLOCK4 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI1_BLOCK4_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI1 BLOCK4 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI2_BLOCK1_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI2 BLOCK1 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI2_BLOCK1_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI2 BLOCK1 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI2_BLOCK1_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI2 BLOCK1 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI2_BLOCK2_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI2 BLOCK2 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI2_BLOCK2_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI2 BLOCK2 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI2_BLOCK2_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI2 BLOCK2 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI2_BLOCK3_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI2 BLOCK3 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI2_BLOCK3_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI2 BLOCK3 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI2_BLOCK3_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI2 BLOCK3 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_WADI2_BLOCK4_SIG1ERROR_BUS_O_0", displayName: "EVENT WADI2 BLOCK4 SIG1ERROR BUS O 0" },
	{ name: "ESM_EVENT_WADI2_BLOCK4_SIG2ERROR_BUS_O_1", displayName: "EVENT WADI2 BLOCK4 SIG2ERROR BUS O 1" },
	{ name: "ESM_EVENT_WADI2_BLOCK4_SIG_TO_SIGERROR_BUS_O_2", displayName: "EVENT WADI2 BLOCK4 SIG TO SIGERROR BUS O 2" },
	{ name: "ESM_EVENT_EQEPERR", displayName: "EVENT EQEPERR" },
	{ name: "ESM_EVENT_CPU1_OVFINT", displayName: "EVENT CPU1 OVFINT" },
	{ name: "ESM_EVENT_CPU1_UVFINT", displayName: "EVENT CPU1 UVFINT" },
	{ name: "ESM_EVENT_CPU1_DOVINT", displayName: "EVENT CPU1 DOVINT" },
	{ name: "ESM_EVENT_CPU2_OVFINT", displayName: "EVENT CPU2 OVFINT" },
	{ name: "ESM_EVENT_CPU2_UVFINT", displayName: "EVENT CPU2 UVFINT" },
	{ name: "ESM_EVENT_CPU2_DOVINT", displayName: "EVENT CPU2 DOVINT" },
	{ name: "ESM_EVENT_CPU3_OVFINT", displayName: "EVENT CPU3 OVFINT" },
	{ name: "ESM_EVENT_CPU3_UVFINT", displayName: "EVENT CPU3 UVFINT" },
	{ name: "ESM_EVENT_CPU3_DOVINT", displayName: "EVENT CPU3 DOVINT" },
	{ name: "ESM_EVENT_MEMSS_REG_PAR_ERR", displayName: "EVENT MEMSS REG PAR ERR" },
	{ name: "ESM_EVENT_FRI_REG_PAR_ERR", displayName: "EVENT FRI REG PAR ERR" },
	{ name: "ESM_EVENT_SYSCTL_REG_PAR_ERR", displayName: "EVENT SYSCTL REG PAR ERR" },
	{ name: "ESM_EVENT_LCM_CPU1SS_REG_PAR_ERR", displayName: "EVENT LCM CPU1SS REG PAR ERR" },
	{ name: "ESM_EVENT_LCM_RTDMA_REG_PAR_ERR", displayName: "EVENT LCM RTDMA REG PAR ERR" },
	{ name: "ESM_EVENT_WADI_REG_PAR_ERR", displayName: "EVENT WADI REG PAR ERR" },
	{ name: "ESM_EVENT_CPU1_TMUROM_PAR_ERR", displayName: "EVENT CPU1 TMUROM PAR ERR" },
	{ name: "ESM_EVENT_CPU2_TMUROM_PAR_ERR", displayName: "EVENT CPU2 TMUROM PAR ERR" },
	{ name: "ESM_EVENT_CPU3_TMUROM_PAR_ERR", displayName: "EVENT CPU3 TMUROM PAR ERR" },
]
let ESM_EOIVector = [
	{ name: "ESM_EOI_CONFIG_ERROR_INTERRUPT", displayName: "EOI CONFIG ERROR INTERRUPT" },
	{ name: "ESM_EOI_LOW_PRIORITY_ERROR_INTERRUPT", displayName: "EOI LOW PRIORITY ERROR INTERRUPT" },
	{ name: "ESM_EOI_HIGH_PRIORITY_ERROR_INTERRUPT", displayName: "EOI HIGH PRIORITY ERROR INTERRUPT" },
	{ name: "ESM_EOI_HIGH_PRIORITY_WATCHDOG_INTERRUPT", displayName: "EOI HIGH PRIORITY WATCHDOG INTERRUPT" },
	{ name: "ESM_EOI_ERROR_PIN_MONITOR_INTERRUPT", displayName: "EOI ERROR PIN MONITOR INTERRUPT" },
]
let ESM_OutputPinMode = [
	{ name: "ESM_OUTPUT_LEVEL_MODE", displayName: "Level mode" },
	{ name: "ESM_OUTPUT_PWM_MODE", displayName: "PWM mode" },
]
let ESM_OperationMode = [
	{ name: "ESM_NORMAL_MODE", displayName: "ESM Normal mode of operation" },
	{ name: "ESM_ERROR_FORCE_MODE", displayName: "ESM Error force mode of operation" },
	{ name: "ESM_CLEAR_EVENT", displayName: "Clear event (returns to Normal Mode (4’b0000) on the next cycle.)" },
]
let ESM_LevelModePolarity = [
	{ name: "ESM_LEVEL_POLARITY_ACTIVE_LOW", displayName: "The error output pin in level mode is active low (default)." },
	{ name: "ESM_LEVEL_POLARITY_ACTIVE_HIGH", displayName: "The polarity of error output pin is active high." },
]
let ESM_InterruptPriorityLevel = [
	{ name: "ESM_INTERRUPT_PRIORITY_LEVEL_LOW", displayName: "Configure interrupt priority level to low priority" },
	{ name: "ESM_INTERRUPT_PRIORITY_LEVEL_HIGH", displayName: "Configure interrupt priority level to high priority" },
]
let ESM_EventGroup = [
	{ name: "ESM_EVENT_GROUP_1", displayName: "EVENT GROUP 1" },
	{ name: "ESM_EVENT_GROUP_2", displayName: "EVENT GROUP 2" },
	{ name: "ESM_EVENT_GROUP_3", displayName: "EVENT GROUP 3" },
	{ name: "ESM_EVENT_GROUP_4", displayName: "EVENT GROUP 4" },
	{ name: "ESM_EVENT_GROUP_5", displayName: "EVENT GROUP 5" },
	{ name: "ESM_EVENT_GROUP_6", displayName: "EVENT GROUP 6" },
	{ name: "ESM_EVENT_GROUP_7", displayName: "EVENT GROUP 7" },
	{ name: "ESM_EVENT_GROUP_8", displayName: "EVENT GROUP 8" },
]
let ESM_GLOBAL = [
	{ name: "ESM_GLOBAL_ENABLE", displayName: "GLOBAL ENABLE" },
	{ name: "ESM_GLOBAL_DISABLE", displayName: "GLOBAL DISABLE" },
]
let ESM_WATCHDOG = [
	{ name: "ESM_WATCHDOG_ENABLE", displayName: "WATCHDOG ENABLE" },
	{ name: "ESM_WATCHDOG_DISABLE", displayName: "WATCHDOG DISABLE" },
]
let ESM_ERROR_PIN_MONITOR = [
	{ name: "ESM_ERROR_PIN_MONITOR_ENABLE", displayName: "MONITOR ENABLE" },
	{ name: "ESM_ERROR_PIN_MONITOR_DISABLE", displayName: "MONITOR DISABLE" },
]
module.exports = {
	ESM_EventMap: ESM_EventMap,
	ESM_EOIVector: ESM_EOIVector,
	ESM_OutputPinMode: ESM_OutputPinMode,
	ESM_OperationMode: ESM_OperationMode,
	ESM_LevelModePolarity: ESM_LevelModePolarity,
	ESM_InterruptPriorityLevel: ESM_InterruptPriorityLevel,
	ESM_EventGroup: ESM_EventGroup,
	ESM_GLOBAL: ESM_GLOBAL,
	ESM_WATCHDOG: ESM_WATCHDOG,
	ESM_ERROR_PIN_MONITOR: ESM_ERROR_PIN_MONITOR,
}
