let Sysctl_PLLClockSource = [
	{ name: "SYSCTL_OSCSRC_OSC2", displayName: "Internal Oscillator 2" },
	{ name: "SYSCTL_OSCSRC_XTAL", displayName: "External XTAL" },
	{ name: "SYSCTL_OSCSRC_XTAL_SE", displayName: "External XTAL Single-ended mode" },
	{ name: "SYSCTL_OSCSRC_OSC1", displayName: "Internal Oscillator 1" },
]
let Sysctl_PLLConfig = [
	{ name: "SYSCTL_PLL_ENABLE", displayName: "PLL ENABLE" },
	{ name: "SYSCTL_PLL_DISABLE", displayName: "PLL DISABLE" },
	{ name: "SYSCTL_PLL_BYPASS", displayName: "PLL BYPASS" },
]
let Sysctl_PLLRefDiv = [
	{ name: "SYSCTL_REFDIV_1", displayName: "1" },
	{ name: "SYSCTL_REFDIV_2", displayName: "2" },
	{ name: "SYSCTL_REFDIV_3", displayName: "3" },
	{ name: "SYSCTL_REFDIV_4", displayName: "4" },
	{ name: "SYSCTL_REFDIV_5", displayName: "5" },
	{ name: "SYSCTL_REFDIV_6", displayName: "6" },
	{ name: "SYSCTL_REFDIV_7", displayName: "7" },
	{ name: "SYSCTL_REFDIV_8", displayName: "8" },
	{ name: "SYSCTL_REFDIV_9", displayName: "9" },
	{ name: "SYSCTL_REFDIV_10", displayName: "10" },
	{ name: "SYSCTL_REFDIV_11", displayName: "11" },
	{ name: "SYSCTL_REFDIV_12", displayName: "12" },
	{ name: "SYSCTL_REFDIV_13", displayName: "13" },
	{ name: "SYSCTL_REFDIV_14", displayName: "14" },
	{ name: "SYSCTL_REFDIV_15", displayName: "15" },
	{ name: "SYSCTL_REFDIV_16", displayName: "16" },
	{ name: "SYSCTL_REFDIV_17", displayName: "17" },
	{ name: "SYSCTL_REFDIV_18", displayName: "18" },
	{ name: "SYSCTL_REFDIV_19", displayName: "19" },
	{ name: "SYSCTL_REFDIV_20", displayName: "20" },
	{ name: "SYSCTL_REFDIV_21", displayName: "21" },
	{ name: "SYSCTL_REFDIV_22", displayName: "22" },
	{ name: "SYSCTL_REFDIV_23", displayName: "23" },
	{ name: "SYSCTL_REFDIV_24", displayName: "24" },
	{ name: "SYSCTL_REFDIV_25", displayName: "25" },
	{ name: "SYSCTL_REFDIV_26", displayName: "26" },
	{ name: "SYSCTL_REFDIV_27", displayName: "27" },
	{ name: "SYSCTL_REFDIV_28", displayName: "28" },
	{ name: "SYSCTL_REFDIV_29", displayName: "29" },
	{ name: "SYSCTL_REFDIV_30", displayName: "30" },
	{ name: "SYSCTL_REFDIV_31", displayName: "31" },
	{ name: "SYSCTL_REFDIV_32", displayName: "32" },
]
let Sysctl_PLLIMult = [
	{ name: "SYSCTL_IMULT_4", displayName: "4" },
	{ name: "SYSCTL_IMULT_5", displayName: "5" },
	{ name: "SYSCTL_IMULT_6", displayName: "6" },
	{ name: "SYSCTL_IMULT_7", displayName: "7" },
	{ name: "SYSCTL_IMULT_8", displayName: "8" },
	{ name: "SYSCTL_IMULT_9", displayName: "9" },
	{ name: "SYSCTL_IMULT_10", displayName: "10" },
	{ name: "SYSCTL_IMULT_11", displayName: "11" },
	{ name: "SYSCTL_IMULT_12", displayName: "12" },
	{ name: "SYSCTL_IMULT_13", displayName: "13" },
	{ name: "SYSCTL_IMULT_14", displayName: "14" },
	{ name: "SYSCTL_IMULT_15", displayName: "15" },
	{ name: "SYSCTL_IMULT_16", displayName: "16" },
	{ name: "SYSCTL_IMULT_17", displayName: "17" },
	{ name: "SYSCTL_IMULT_18", displayName: "18" },
	{ name: "SYSCTL_IMULT_19", displayName: "19" },
	{ name: "SYSCTL_IMULT_20", displayName: "20" },
	{ name: "SYSCTL_IMULT_21", displayName: "21" },
	{ name: "SYSCTL_IMULT_22", displayName: "22" },
	{ name: "SYSCTL_IMULT_23", displayName: "23" },
	{ name: "SYSCTL_IMULT_24", displayName: "24" },
	{ name: "SYSCTL_IMULT_25", displayName: "25" },
	{ name: "SYSCTL_IMULT_26", displayName: "26" },
	{ name: "SYSCTL_IMULT_27", displayName: "27" },
	{ name: "SYSCTL_IMULT_28", displayName: "28" },
	{ name: "SYSCTL_IMULT_29", displayName: "29" },
	{ name: "SYSCTL_IMULT_30", displayName: "30" },
	{ name: "SYSCTL_IMULT_31", displayName: "31" },
	{ name: "SYSCTL_IMULT_32", displayName: "32" },
	{ name: "SYSCTL_IMULT_33", displayName: "33" },
	{ name: "SYSCTL_IMULT_34", displayName: "34" },
	{ name: "SYSCTL_IMULT_35", displayName: "35" },
	{ name: "SYSCTL_IMULT_36", displayName: "36" },
	{ name: "SYSCTL_IMULT_37", displayName: "37" },
	{ name: "SYSCTL_IMULT_38", displayName: "38" },
	{ name: "SYSCTL_IMULT_39", displayName: "39" },
	{ name: "SYSCTL_IMULT_40", displayName: "40" },
	{ name: "SYSCTL_IMULT_41", displayName: "41" },
	{ name: "SYSCTL_IMULT_42", displayName: "42" },
	{ name: "SYSCTL_IMULT_43", displayName: "43" },
	{ name: "SYSCTL_IMULT_44", displayName: "44" },
	{ name: "SYSCTL_IMULT_45", displayName: "45" },
	{ name: "SYSCTL_IMULT_46", displayName: "46" },
	{ name: "SYSCTL_IMULT_47", displayName: "47" },
	{ name: "SYSCTL_IMULT_48", displayName: "48" },
	{ name: "SYSCTL_IMULT_49", displayName: "49" },
	{ name: "SYSCTL_IMULT_50", displayName: "50" },
	{ name: "SYSCTL_IMULT_51", displayName: "51" },
	{ name: "SYSCTL_IMULT_52", displayName: "52" },
	{ name: "SYSCTL_IMULT_53", displayName: "53" },
	{ name: "SYSCTL_IMULT_54", displayName: "54" },
	{ name: "SYSCTL_IMULT_55", displayName: "55" },
	{ name: "SYSCTL_IMULT_56", displayName: "56" },
	{ name: "SYSCTL_IMULT_57", displayName: "57" },
	{ name: "SYSCTL_IMULT_58", displayName: "58" },
	{ name: "SYSCTL_IMULT_59", displayName: "59" },
	{ name: "SYSCTL_IMULT_60", displayName: "60" },
	{ name: "SYSCTL_IMULT_61", displayName: "61" },
	{ name: "SYSCTL_IMULT_62", displayName: "62" },
	{ name: "SYSCTL_IMULT_63", displayName: "63" },
	{ name: "SYSCTL_IMULT_64", displayName: "64" },
	{ name: "SYSCTL_IMULT_65", displayName: "65" },
	{ name: "SYSCTL_IMULT_66", displayName: "66" },
	{ name: "SYSCTL_IMULT_67", displayName: "67" },
	{ name: "SYSCTL_IMULT_68", displayName: "68" },
	{ name: "SYSCTL_IMULT_69", displayName: "69" },
	{ name: "SYSCTL_IMULT_70", displayName: "70" },
	{ name: "SYSCTL_IMULT_71", displayName: "71" },
	{ name: "SYSCTL_IMULT_72", displayName: "72" },
	{ name: "SYSCTL_IMULT_73", displayName: "73" },
	{ name: "SYSCTL_IMULT_74", displayName: "74" },
	{ name: "SYSCTL_IMULT_75", displayName: "75" },
	{ name: "SYSCTL_IMULT_76", displayName: "76" },
	{ name: "SYSCTL_IMULT_77", displayName: "77" },
	{ name: "SYSCTL_IMULT_78", displayName: "78" },
	{ name: "SYSCTL_IMULT_79", displayName: "79" },
	{ name: "SYSCTL_IMULT_80", displayName: "80" },
	{ name: "SYSCTL_IMULT_81", displayName: "81" },
	{ name: "SYSCTL_IMULT_82", displayName: "82" },
	{ name: "SYSCTL_IMULT_83", displayName: "83" },
	{ name: "SYSCTL_IMULT_84", displayName: "84" },
	{ name: "SYSCTL_IMULT_85", displayName: "85" },
	{ name: "SYSCTL_IMULT_86", displayName: "86" },
	{ name: "SYSCTL_IMULT_87", displayName: "87" },
	{ name: "SYSCTL_IMULT_88", displayName: "88" },
	{ name: "SYSCTL_IMULT_89", displayName: "89" },
	{ name: "SYSCTL_IMULT_90", displayName: "90" },
	{ name: "SYSCTL_IMULT_91", displayName: "91" },
	{ name: "SYSCTL_IMULT_92", displayName: "92" },
	{ name: "SYSCTL_IMULT_93", displayName: "93" },
	{ name: "SYSCTL_IMULT_94", displayName: "94" },
	{ name: "SYSCTL_IMULT_95", displayName: "95" },
	{ name: "SYSCTL_IMULT_96", displayName: "96" },
	{ name: "SYSCTL_IMULT_97", displayName: "97" },
	{ name: "SYSCTL_IMULT_98", displayName: "98" },
	{ name: "SYSCTL_IMULT_99", displayName: "99" },
	{ name: "SYSCTL_IMULT_100", displayName: "100" },
	{ name: "SYSCTL_IMULT_101", displayName: "101" },
	{ name: "SYSCTL_IMULT_102", displayName: "102" },
	{ name: "SYSCTL_IMULT_103", displayName: "103" },
	{ name: "SYSCTL_IMULT_104", displayName: "104" },
	{ name: "SYSCTL_IMULT_105", displayName: "105" },
	{ name: "SYSCTL_IMULT_106", displayName: "106" },
	{ name: "SYSCTL_IMULT_107", displayName: "107" },
	{ name: "SYSCTL_IMULT_108", displayName: "108" },
	{ name: "SYSCTL_IMULT_109", displayName: "109" },
	{ name: "SYSCTL_IMULT_110", displayName: "110" },
	{ name: "SYSCTL_IMULT_111", displayName: "111" },
	{ name: "SYSCTL_IMULT_112", displayName: "112" },
	{ name: "SYSCTL_IMULT_113", displayName: "113" },
	{ name: "SYSCTL_IMULT_114", displayName: "114" },
	{ name: "SYSCTL_IMULT_115", displayName: "115" },
	{ name: "SYSCTL_IMULT_116", displayName: "116" },
	{ name: "SYSCTL_IMULT_117", displayName: "117" },
	{ name: "SYSCTL_IMULT_118", displayName: "118" },
	{ name: "SYSCTL_IMULT_119", displayName: "119" },
	{ name: "SYSCTL_IMULT_120", displayName: "120" },
	{ name: "SYSCTL_IMULT_121", displayName: "121" },
	{ name: "SYSCTL_IMULT_122", displayName: "122" },
	{ name: "SYSCTL_IMULT_123", displayName: "123" },
	{ name: "SYSCTL_IMULT_124", displayName: "124" },
	{ name: "SYSCTL_IMULT_125", displayName: "125" },
	{ name: "SYSCTL_IMULT_126", displayName: "126" },
	{ name: "SYSCTL_IMULT_127", displayName: "127" },
]
let Sysctl_PLLODiv = [
	{ name: "SYSCTL_ODIV_1", displayName: "1" },
	{ name: "SYSCTL_ODIV_2", displayName: "2" },
	{ name: "SYSCTL_ODIV_3", displayName: "3" },
	{ name: "SYSCTL_ODIV_4", displayName: "4" },
	{ name: "SYSCTL_ODIV_5", displayName: "5" },
	{ name: "SYSCTL_ODIV_6", displayName: "6" },
	{ name: "SYSCTL_ODIV_7", displayName: "7" },
	{ name: "SYSCTL_ODIV_8", displayName: "8" },
	{ name: "SYSCTL_ODIV_9", displayName: "9" },
	{ name: "SYSCTL_ODIV_10", displayName: "10" },
	{ name: "SYSCTL_ODIV_11", displayName: "11" },
	{ name: "SYSCTL_ODIV_12", displayName: "12" },
	{ name: "SYSCTL_ODIV_13", displayName: "13" },
	{ name: "SYSCTL_ODIV_14", displayName: "14" },
	{ name: "SYSCTL_ODIV_15", displayName: "15" },
	{ name: "SYSCTL_ODIV_16", displayName: "16" },
	{ name: "SYSCTL_ODIV_17", displayName: "17" },
	{ name: "SYSCTL_ODIV_18", displayName: "18" },
	{ name: "SYSCTL_ODIV_19", displayName: "19" },
	{ name: "SYSCTL_ODIV_20", displayName: "20" },
	{ name: "SYSCTL_ODIV_21", displayName: "21" },
	{ name: "SYSCTL_ODIV_22", displayName: "22" },
	{ name: "SYSCTL_ODIV_23", displayName: "23" },
	{ name: "SYSCTL_ODIV_24", displayName: "24" },
	{ name: "SYSCTL_ODIV_25", displayName: "25" },
	{ name: "SYSCTL_ODIV_26", displayName: "26" },
	{ name: "SYSCTL_ODIV_27", displayName: "27" },
	{ name: "SYSCTL_ODIV_28", displayName: "28" },
	{ name: "SYSCTL_ODIV_29", displayName: "29" },
	{ name: "SYSCTL_ODIV_30", displayName: "30" },
	{ name: "SYSCTL_ODIV_31", displayName: "31" },
	{ name: "SYSCTL_ODIV_32", displayName: "32" },
]
let Sysctl_PLLSysDiv = [
	{ name: "SYSCTL_SYSDIV_1", displayName: "1" },
	{ name: "SYSCTL_SYSDIV_2", displayName: "2" },
	{ name: "SYSCTL_SYSDIV_3", displayName: "3" },
	{ name: "SYSCTL_SYSDIV_4", displayName: "4" },
	{ name: "SYSCTL_SYSDIV_5", displayName: "5" },
	{ name: "SYSCTL_SYSDIV_6", displayName: "6" },
	{ name: "SYSCTL_SYSDIV_7", displayName: "7" },
	{ name: "SYSCTL_SYSDIV_8", displayName: "8" },
	{ name: "SYSCTL_SYSDIV_9", displayName: "9" },
	{ name: "SYSCTL_SYSDIV_10", displayName: "10" },
	{ name: "SYSCTL_SYSDIV_11", displayName: "11" },
	{ name: "SYSCTL_SYSDIV_12", displayName: "12" },
	{ name: "SYSCTL_SYSDIV_13", displayName: "13" },
	{ name: "SYSCTL_SYSDIV_14", displayName: "14" },
	{ name: "SYSCTL_SYSDIV_15", displayName: "15" },
	{ name: "SYSCTL_SYSDIV_16", displayName: "16" },
	{ name: "SYSCTL_SYSDIV_17", displayName: "17" },
	{ name: "SYSCTL_SYSDIV_18", displayName: "18" },
	{ name: "SYSCTL_SYSDIV_19", displayName: "19" },
	{ name: "SYSCTL_SYSDIV_20", displayName: "20" },
	{ name: "SYSCTL_SYSDIV_21", displayName: "21" },
	{ name: "SYSCTL_SYSDIV_22", displayName: "22" },
	{ name: "SYSCTL_SYSDIV_23", displayName: "23" },
	{ name: "SYSCTL_SYSDIV_24", displayName: "24" },
	{ name: "SYSCTL_SYSDIV_25", displayName: "25" },
	{ name: "SYSCTL_SYSDIV_26", displayName: "26" },
	{ name: "SYSCTL_SYSDIV_27", displayName: "27" },
	{ name: "SYSCTL_SYSDIV_28", displayName: "28" },
	{ name: "SYSCTL_SYSDIV_29", displayName: "29" },
	{ name: "SYSCTL_SYSDIV_30", displayName: "30" },
	{ name: "SYSCTL_SYSDIV_31", displayName: "31" },
	{ name: "SYSCTL_SYSDIV_32", displayName: "32" },
	{ name: "SYSCTL_SYSDIV_33", displayName: "33" },
	{ name: "SYSCTL_SYSDIV_34", displayName: "34" },
	{ name: "SYSCTL_SYSDIV_35", displayName: "35" },
	{ name: "SYSCTL_SYSDIV_36", displayName: "36" },
	{ name: "SYSCTL_SYSDIV_37", displayName: "37" },
	{ name: "SYSCTL_SYSDIV_38", displayName: "38" },
	{ name: "SYSCTL_SYSDIV_39", displayName: "39" },
	{ name: "SYSCTL_SYSDIV_40", displayName: "40" },
	{ name: "SYSCTL_SYSDIV_41", displayName: "41" },
	{ name: "SYSCTL_SYSDIV_42", displayName: "42" },
	{ name: "SYSCTL_SYSDIV_43", displayName: "43" },
	{ name: "SYSCTL_SYSDIV_44", displayName: "44" },
	{ name: "SYSCTL_SYSDIV_45", displayName: "45" },
	{ name: "SYSCTL_SYSDIV_46", displayName: "46" },
	{ name: "SYSCTL_SYSDIV_47", displayName: "47" },
	{ name: "SYSCTL_SYSDIV_48", displayName: "48" },
	{ name: "SYSCTL_SYSDIV_49", displayName: "49" },
	{ name: "SYSCTL_SYSDIV_50", displayName: "50" },
	{ name: "SYSCTL_SYSDIV_51", displayName: "51" },
	{ name: "SYSCTL_SYSDIV_52", displayName: "52" },
	{ name: "SYSCTL_SYSDIV_53", displayName: "53" },
	{ name: "SYSCTL_SYSDIV_54", displayName: "54" },
	{ name: "SYSCTL_SYSDIV_55", displayName: "55" },
	{ name: "SYSCTL_SYSDIV_56", displayName: "56" },
	{ name: "SYSCTL_SYSDIV_57", displayName: "57" },
	{ name: "SYSCTL_SYSDIV_58", displayName: "58" },
	{ name: "SYSCTL_SYSDIV_59", displayName: "59" },
	{ name: "SYSCTL_SYSDIV_60", displayName: "60" },
	{ name: "SYSCTL_SYSDIV_61", displayName: "61" },
	{ name: "SYSCTL_SYSDIV_62", displayName: "62" },
	{ name: "SYSCTL_SYSDIV_63", displayName: "63" },
	{ name: "SYSCTL_SYSDIV_64", displayName: "64" },
]
let SysCtl_XClkSource = [
	{ name: "SYSCTL_XCLKOUT_SOURCE_PLLSYS", displayName: "PLL System Clock post SYSCLKDIV" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_CPU1CLK", displayName: "CPU1.CLOCK" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_CPU2CLK", displayName: "CPU2.CLOCK" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_CPU3CLK", displayName: "CPU3.CLOCK" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_INTOSC1", displayName: "Internal Oscillator 1" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_INTOSC2", displayName: "Internal Oscillator 2" },
	{ name: "SYSCTL_XCLKOUT_SOURCE_XTALOSC", displayName: "External Oscillator" },
]
let SysCtl_XClkDivider = [
	{ name: "SYSCTL_XCLKOUT_DIV_1", displayName: "XCLKOUT =  XCLKOUT source / 1" },
	{ name: "SYSCTL_XCLKOUT_DIV_2", displayName: "XCLKOUT =  XCLKOUT source / 2" },
	{ name: "SYSCTL_XCLKOUT_DIV_4", displayName: "XCLKOUT =  XCLKOUT source / 4" },
	{ name: "SYSCTL_XCLKOUT_DIV_8", displayName: "XCLKOUT =  XCLKOUT source / 8" },
]
let SysCtl_MCANInstance = [
	{ name: "SYSCTL_MCAN_A", displayName: "MCAN A" },
	{ name: "SYSCTL_MCAN_B", displayName: "MCAN B" },
	{ name: "SYSCTL_MCAN_C", displayName: "MCAN C" },
	{ name: "SYSCTL_MCAN_D", displayName: "MCAN D" },
	{ name: "SYSCTL_MCAN_E", displayName: "MCAN E" },
	{ name: "SYSCTL_MCAN_F", displayName: "MCAN F" },
]
let SysCtl_MCANClkSource = [
	{ name: "SYSCTL_MCANCLK_SOURCE_SYS", displayName: "Peripheral System Clock Source" },
	{ name: "SYSCTL_MCANCLK_SOURCE_AUXIN", displayName: "Auxiliary Clock Input Source (GPIO)" },
	{ name: "SYSCTL_MCANCLK_SOURCE_PLLRAW", displayName: "PLL Raw Clock Source" },
]
let SysCtl_MCANClkDivider = [
	{ name: "SYSCTL_MCANCLK_DIV_1", displayName: "MCAN clock =  MCAN clock source / 1" },
	{ name: "SYSCTL_MCANCLK_DIV_2", displayName: "MCAN clock =  MCAN clock source / 2" },
	{ name: "SYSCTL_MCANCLK_DIV_3", displayName: "MCAN clock =  MCAN clock source / 3" },
	{ name: "SYSCTL_MCANCLK_DIV_4", displayName: "MCAN clock =  MCAN clock source / 4" },
	{ name: "SYSCTL_MCANCLK_DIV_5", displayName: "MCAN clock =  MCAN clock source / 5" },
	{ name: "SYSCTL_MCANCLK_DIV_6", displayName: "MCAN clock =  MCAN clock source / 6" },
	{ name: "SYSCTL_MCANCLK_DIV_7", displayName: "MCAN clock =  MCAN clock source / 7" },
	{ name: "SYSCTL_MCANCLK_DIV_8", displayName: "MCAN clock =  MCAN clock source / 8" },
	{ name: "SYSCTL_MCANCLK_DIV_9", displayName: "MCAN clock =  MCAN clock source / 9" },
	{ name: "SYSCTL_MCANCLK_DIV_10", displayName: "MCAN clock =  MCAN clock source / 10" },
	{ name: "SYSCTL_MCANCLK_DIV_11", displayName: "MCAN clock =  MCAN clock source / 11" },
	{ name: "SYSCTL_MCANCLK_DIV_12", displayName: "MCAN clock =  MCAN clock source / 12" },
	{ name: "SYSCTL_MCANCLK_DIV_13", displayName: "MCAN clock =  MCAN clock source / 13" },
	{ name: "SYSCTL_MCANCLK_DIV_14", displayName: "MCAN clock =  MCAN clock source / 14" },
	{ name: "SYSCTL_MCANCLK_DIV_15", displayName: "MCAN clock =  MCAN clock source / 15" },
	{ name: "SYSCTL_MCANCLK_DIV_16", displayName: "MCAN clock =  MCAN clock source / 16" },
	{ name: "SYSCTL_MCANCLK_DIV_17", displayName: "MCAN clock =  MCAN clock source / 17" },
	{ name: "SYSCTL_MCANCLK_DIV_18", displayName: "MCAN clock =  MCAN clock source / 18" },
	{ name: "SYSCTL_MCANCLK_DIV_19", displayName: "MCAN clock =  MCAN clock source / 19" },
	{ name: "SYSCTL_MCANCLK_DIV_20", displayName: "MCAN clock =  MCAN clock source / 20" },
]
let SysCtl_Cputimer2ClkSource = [
	{ name: "SYSCTL_TIMER2CLK_SOURCE_SYSCLK", displayName: "System Clock" },
	{ name: "SYSCTL_TIMER2CLK_SOURCE_INTOSC1", displayName: "Internal Oscillator 1" },
	{ name: "SYSCTL_TIMER2CLK_SOURCE_INTOSC2", displayName: "Internal Oscillator 2" },
	{ name: "SYSCTL_TIMER2CLK_SOURCE_XTAL", displayName: "Crystal oscillator" },
]
let SysCtl_Cputimer2ClkDivider = [
	{ name: "SYSCTL_TIMER2CLK_DIV_1", displayName: "Cputimer2 clock =  Cputimer2 clock / 1" },
	{ name: "SYSCTL_TIMER2CLK_DIV_2", displayName: "Cputimer2 clock =  Cputimer2 clock / 2" },
	{ name: "SYSCTL_TIMER2CLK_DIV_4", displayName: "Cputimer2 clock =  Cputimer2 clock / 4" },
	{ name: "SYSCTL_TIMER2CLK_DIV_8", displayName: "Cputimer2 clock =  Cputimer2 clock / 8" },
	{ name: "SYSCTL_TIMER2CLK_DIV_16", displayName: "Cputimer2 clock =  Cputimer2 clock / 16" },
]
let SysCtl_EPWMClkDivider = [
	{ name: "SYSCTL_EPWMCLK_DIV_1", displayName: "EPWMCLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_EPWMCLK_DIV_2", displayName: "EPWMCLK = PLLSYSCLK / 2" },
]
let SysCtl_EMIFClkDivider = [
	{ name: "SYSCTL_EMIFCLK_DIV_1", displayName: "EMIF1CLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_EMIFCLK_DIV_2", displayName: "EMIF1CLK = PLLSYSCLK / 2" },
	{ name: "SYSCTL_EMIFCLK_DIV_4", displayName: "EMIF1CLK = PLLSYSCLK / 4" },
]
let SysCtl_LINClkDivider = [
	{ name: "SYSCTL_LINCLK_DIV_1", displayName: "LINACLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_LINCLK_DIV_2", displayName: "LINACLK = PLLSYSCLK / 2" },
	{ name: "SYSCTL_LINCLK_DIV_4", displayName: "LINACLK = PLLSYSCLK / 4" },
]
let SysCtl_ECatClkDivider = [
	{ name: "SYSCTL_ECATCLKOUT_DIV_1", displayName: "ECat clock =  PLLCLK / 1" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_2", displayName: "ECat clock =  PLLCLK / 2" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_3", displayName: "ECat clock =  PLLCLK / 3" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_4", displayName: "ECat clock =  PLLCLK / 4" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_5", displayName: "ECat clock =  PLLCLK / 5" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_6", displayName: "ECat clock =  PLLCLK / 6" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_7", displayName: "ECat clock =  PLLCLK / 7" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_8", displayName: "ECat clock =  PLLCLK / 8" },
]
let SysCtl_ECatPhyClk = [
	{ name: "SYSCTL_ECAT_PHYCLK_ENABLE", displayName: "ECAT PHYCLK ENABLE" },
	{ name: "SYSCTL_ECAT_PHYCLK_DISABLE", displayName: "ECAT PHYCLK DISABLE" },
]
let SysCtl_CLBClkDivider = [
	{ name: "SYSCTL_CLBCLKOUT_DIV_1", displayName: "CLB clock =  CLB clock / 1" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_2", displayName: "CLB clock =  CLB clock / 2" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_3", displayName: "CLB clock =  CLB clock / 3" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_4", displayName: "CLB clock =  CLB clock / 4" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_5", displayName: "CLB clock =  CLB clock / 5" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_6", displayName: "CLB clock =  CLB clock / 6" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_7", displayName: "CLB clock =  CLB clock / 7" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_8", displayName: "CLB clock =  CLB clock / 8" },
]
let SysCtl_CLBTClkDivider = [
	{ name: "SYSCTL_CLBTCLKOUT_DIV_1", displayName: "CLBTCLKOUT =  CLB clock / 1" },
	{ name: "SYSCTL_CLBTCLKOUT_DIV_2", displayName: "CLBTCLKOUT =  CLB clock / 2" },
]
let SysCtl_HSMClkDivider = [
	{ name: "SYSCTL_HSMCLK_DIV_1", displayName: "HSM Clock =  HSM clock / 1" },
	{ name: "SYSCTL_HSMCLK_DIV_2", displayName: "HSM Clock =  HSM clock / 2" },
	{ name: "SYSCTL_HSMCLK_DIV_4", displayName: "HSM Clock =  HSM clock / 4" },
	{ name: "SYSCTL_HSMCLK_DIV_8", displayName: "HSM Clock =  HSM clock / 8" },
	{ name: "SYSCTL_HSMCLK_DIV_16", displayName: "HSM Clock =  HSM clock / 16" },
]
let CLOCK_H = [
	{ name: "CLOCK_H", displayName: "H" },
]
let SYSCTL_DEFAULT_OSC_FREQ = [
	{ name: "SYSCTL_DEFAULT_OSC_FREQ", displayName: "FREQ" },
]
let SYSCTL_CLB = [
	{ name: "SYSCTL_CLB1CLKMODE_SYNC", displayName: "CLB1CLKMODE SYNC" },
	{ name: "SYSCTL_CLB1CLKMODE_ASYNC", displayName: "CLB1CLKMODE ASYNC" },
	{ name: "SYSCTL_CLB2CLKMODE_SYNC", displayName: "CLB2CLKMODE SYNC" },
	{ name: "SYSCTL_CLB2CLKMODE_ASYNC", displayName: "CLB2CLKMODE ASYNC" },
	{ name: "SYSCTL_CLB3CLKMODE_SYNC", displayName: "CLB3CLKMODE SYNC" },
	{ name: "SYSCTL_CLB3CLKMODE_ASYNC", displayName: "CLB3CLKMODE ASYNC" },
	{ name: "SYSCTL_CLB4CLKMODE_SYNC", displayName: "CLB4CLKMODE SYNC" },
	{ name: "SYSCTL_CLB4CLKMODE_ASYNC", displayName: "CLB4CLKMODE ASYNC" },
	{ name: "SYSCTL_CLB5CLKMODE_SYNC", displayName: "CLB5CLKMODE SYNC" },
	{ name: "SYSCTL_CLB5CLKMODE_ASYNC", displayName: "CLB5CLKMODE ASYNC" },
	{ name: "SYSCTL_CLB6CLKMODE_SYNC", displayName: "CLB6CLKMODE SYNC" },
	{ name: "SYSCTL_CLB6CLKMODE_ASYNC", displayName: "CLB6CLKMODE ASYNC" },
]
module.exports = {
	Sysctl_PLLClockSource: Sysctl_PLLClockSource,
	Sysctl_PLLConfig: Sysctl_PLLConfig,
	Sysctl_PLLRefDiv: Sysctl_PLLRefDiv,
	Sysctl_PLLIMult: Sysctl_PLLIMult,
	Sysctl_PLLODiv: Sysctl_PLLODiv,
	Sysctl_PLLSysDiv: Sysctl_PLLSysDiv,
	SysCtl_XClkSource: SysCtl_XClkSource,
	SysCtl_XClkDivider: SysCtl_XClkDivider,
	SysCtl_MCANInstance: SysCtl_MCANInstance,
	SysCtl_MCANClkSource: SysCtl_MCANClkSource,
	SysCtl_MCANClkDivider: SysCtl_MCANClkDivider,
	SysCtl_Cputimer2ClkSource: SysCtl_Cputimer2ClkSource,
	SysCtl_Cputimer2ClkDivider: SysCtl_Cputimer2ClkDivider,
	SysCtl_EPWMClkDivider: SysCtl_EPWMClkDivider,
	SysCtl_EMIFClkDivider: SysCtl_EMIFClkDivider,
	SysCtl_LINClkDivider: SysCtl_LINClkDivider,
	SysCtl_ECatClkDivider: SysCtl_ECatClkDivider,
	SysCtl_ECatPhyClk: SysCtl_ECatPhyClk,
	SysCtl_CLBClkDivider: SysCtl_CLBClkDivider,
	SysCtl_CLBTClkDivider: SysCtl_CLBTClkDivider,
	SysCtl_HSMClkDivider: SysCtl_HSMClkDivider,
	CLOCK_H: CLOCK_H,
	SYSCTL_DEFAULT_OSC_FREQ: SYSCTL_DEFAULT_OSC_FREQ,
	SYSCTL_CLB: SYSCTL_CLB,
}
