/*
   Copyright (c) 2024 by Plexim GmbH
   All rights reserved.

   A free license is granted to anyone to use this software for any legal
   non safety-critical purpose, including commercial applications, provided
   that:
   1) IT IS NOT USED TO DIRECTLY OR INDIRECTLY COMPETE WITH PLEXIM, and
   2) THIS COPYRIGHT NOTICE IS PRESERVED in its entirety.

   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
   OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   SOFTWARE.
 */

MEMORY
{
   BEGIN            : origin = 0x000000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x000126     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x000128, length = 0x0002D8
   RAMM1            : origin = 0x000400, length = 0x000400
   
   RAMLS            : origin = 0x008000, length = 0x004000
   //RAMLS0           : origin = 0x008000, length = 0x000800
   //RAMLS1           : origin = 0x008800, length = 0x000800
   //RAMLS2           : origin = 0x009000, length = 0x000800
   //RAMLS3           : origin = 0x009800, length = 0x000800
   //RAMLS4           : origin = 0x00A000, length = 0x000800
   //RAMLS5           : origin = 0x00A800, length = 0x000800
   //RAMLS6           : origin = 0x00B000, length = 0x000800
   //RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMLS8           : origin = 0x014000, length = 0x002000  // When configured as CLA program use the address 0x4000
   RAMLS9           : origin = 0x016000, length = 0x002000  // When configured as CLA program use the address 0x6000

   // RAMLS8_CLA    : origin = 0x004000, length = 0x002000  // Use only if configured as CLA program memory
   // RAMLS9_CLA    : origin = 0x006000, length = 0x002000  // Use only if configured as CLA program memory

    PRAMGS            : origin = 0x00C000, length = 0x008000
   //RAMGS0           : origin = 0x00C000, length = 0x002000
   //RAMGS1           : origin = 0x00E000, length = 0x002000
   //RAMGS2           : origin = 0x010000, length = 0x002000
   //RAMGS3           : origin = 0x012000, length = 0x002000

   /* Flash Banks (128 sectors each) */
   //FLASH    : origin = 0x080002, length = 0x1FFFE
   //FLASH_BANK0     : origin = 0x080000, length = 0x20000
   //FLASH_BANK1     : origin = 0x0A0000, length = 0x20000
   //FLASH_BANK2     : origin = 0x0C0000, length = 0x20000
   //FLASH_BANK3     : origin = 0x0E0000, length = 0x20000
   //FLASH_BANK4     : origin = 0x100000, length = 0x20000


   CLATOCPURAM      : origin = 0x001480,   length = 0x000080
   CPUTOCLARAM      : origin = 0x001500,   length = 0x000080
   CLATODMARAM      : origin = 0x001680,   length = 0x000080
   DMATOCLARAM      : origin = 0x001700,   length = 0x000080

   RESET            : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
   scope            : > RAMLS, ALIGN(2)
   step             : > PRAMGS
   dispatch         : > PRAMGS

   codestart        : > BEGIN
   .text            : > PRAMGS
   .cinit           : > PRAMGS
   .switch          : > PRAMGS

   .stack           : > RAMM1 | RAMLS

#if defined(__TI_EABI__)
   .bss             : > RAMLS
   .bss:output      : > RAMLS
   .bss:cio         : > RAMLS
   .init_array      : > PRAMGS
   .const           : > PRAMGS
   .data            : > RAMLS
   .sysmem          : > RAMLS
#else
   .pinit           : > PRAMGS
   .ebss            : > RAMLS
   .cio             : > PRAMGS
   .econst          : > PRAMGS
   .esysmem         : > RAMLS
#endif

   GROUP: > PRAMGS
   {
      ramfuncs
      .TI.ramfunc
   }
   
   .reset              : > RESET, TYPE = DSECT
}
