PIL / HIL Simulation and Advanced Modeling of Power Electronic Systems
08:30 |
Registration |
09:00 |
C-Code Integration
Exercise: Efficient PWM generation using the PLECS C-Script block |
10:15 |
Break |
10:30 |
C-Code Integration (Continuation)
Exercise: Efficient PWM generation using the PLECS C-Script block |
12:00 |
Lunch |
13:00 |
Analysis Tools (Multitone Analysis)
|
14:00 |
Principle of a Processor-in-the-Loop (PIL) Simulation
|
15:00 |
Pause |
15:15 |
Hardware-in-the-Loop (HIL) Simulation using the PLECS RT Box
|
16:00 |
What's New in PLECS / Q&A |
16:30 |
End of Workshop |
This workshop addresses to anyone who already has experience with the simulation software PLECS.
To be announced
Roman Troesch
troesch@plexim.com, +41 (0)44 533 51 18
Warsaw University of Technology
Main Building (Gmach Główny)
Room 443
Pl. Politechniki 1
00-661 Warszawa
Poland