This PLECS demo model shows a 320 kV, 200 MW high-voltage direct current (HVDC) transmission system with two modular multi-level converters (MMC) interconnecting two 110 kV high-voltage AC grids. MMCs are the prevalent type of voltage-source converter topology for HVDC applications. At high voltages the transmission of direct current can be more efficient than alternating current. The MMC is a bi-directional voltage source converter that interfaces high-voltage AC and DC power systems. It comprises a positive and negative arm for each of the three phases. Each arm further contains a set of switching submodules connected in series, the number of which can be chosen in this model to achieve the desired harmonic performance.
Both AC grids are modeled as a three-phase voltage source with series impedance. The MMC connecting the AC system I and the DC system is configured to 38 submodule cells per arm. Each submodule cell is composed of one half-bridge and a DC-link capacitor. As a result, each cell has a maximum voltage of approximately 16.8 kVDC at steady state. Each single-phase pair of converter arms, together with their arm inductors, is connected to the AC system I grid. The converter arms are implemented with the "IGBT Half Bridges (Low-Side-Connected)" power module library component. This component has two configurations: a Switched implementation where ideal switches represent the semiconductors, and an Averaged configuration that uses controlled voltage and current sources. The power module also has a parameter setting for the number of series-connected half-bridge cells. The implementation of both the power module and the controller is such that the number of cells can be configured at the top level without having to extend the model with additional wiring or components.
To make the schematic concise and organized, the IGBTs and DC capacitors are vectorized, instead of displaying 38 cells per arm in the same schematic. The Wire Multiplexer block enables a series connection of half-bridge cells for each of the six arms (2 per phase leg), resulting in only one half-bridge and DC capacitor being visible for each arm, even though 76 cells per phase leg are simulated. The DC sides of the two AC networks are connected via two DC transmission lines, which are modeled using the PI-Section Line component. The converter arms for the MMC on the AC system II grid side are modeled as purely averaged models, similar to the Averaged power module implementation. Equivalent voltage and current sources are employed, however, here, the switching frequency ripple effects are totally neglected. Only one DC-link capacitor is present per arm physically, which represents an average series connection of all cell capacitors. In comparison to the Averaged power module implementation, this design is simpler and increases the simulation speed.
The control scheme of the AC system I MMC can be described in two levels. The top-level control is composed of two loops. An outer loop PI controller regulates the DC transmission voltage and provides the d-axis reference for the inner current control loop. The inner current loop regulates the d- and q-axis grid currents and provides reference voltages for the MMC legs. The low-level modulator is tasked with generating the AC voltage according to the reference and at the same time active balancing of the cell voltages. A cell selection algorithm using vertically shifted carriers is implemented, ensuring that the voltage among all cells of each arm is maintained at approximately the same value. The AC system II MMC only regulates the power flow in the form of the q-axis current. As a purely averaged model without modulated switches is used, only a top-level controller has been realized for this side. The AC voltage reference is directly fed into the six arm modules.
The simulated AC system I converter output voltage, grid current, DC voltage, and positive cell voltages of Arm A are displayed below for the 38-level converter. The user can change the number of cells in the initialization commands to observe the effect of system complexity on simulation speed.
This model is available in the PLECS Demo Model library provided in both versions of PLECS.